X-Git-Url: http://git.joshuawise.com/fpgaboy.git/blobdiff_plain/f888201b9894683abfff012bd68b641319fb2744..68ce013e5fe7c5d1c4e07fe8ba1eb0ba2855b280:/Uart.v

diff --git a/Uart.v b/Uart.v
index af173ca..f9d71f4 100644
--- a/Uart.v
+++ b/Uart.v
@@ -21,14 +21,14 @@ module UART(
 	reg have_data = 0;
 	reg [3:0] diqing = 4'b0000;
 	
-	wire new = (wr) && (!have_data) && decode;
+	wire newdata = (wr) && (!have_data) && decode;
 	
 	assign odata = have_data ? 8'b1 : 8'b0;
 
-	always @ (negedge clk)
+	always @ (posedge clk)
 	begin
 		/* deal with diqing */
-		if(new) begin
+		if(newdata) begin
 			data_stor <= data;
 			have_data <= 1;
 			diqing <= 4'b0000;
@@ -52,7 +52,7 @@ module UART(
 		end
 
 		/* deal with clkdiv */
-		if((new && !have_data) || clkdiv == `CLK_DIV)
+		if((newdata && !have_data) || clkdiv == `CLK_DIV)
 			clkdiv <= 0;
 		else
 			clkdiv <= clkdiv + 1;