Start changing things to happen on posedge clock.
authorJoshua Wise <joshua@rebirth.joshuawise.com>
Sun, 4 May 2008 07:59:43 +0000 (03:59 -0400)
committerJoshua Wise <joshua@rebirth.joshuawise.com>
Sun, 4 May 2008 07:59:43 +0000 (03:59 -0400)
7seg.v
Interrupt.v
Sound1.v
Sound2.v
Soundcore.v
System.v
Timer.v
Uart.v

diff --git a/7seg.v b/7seg.v
index ba988b0..11e26d4 100644 (file)
--- a/7seg.v
+++ b/7seg.v
@@ -25,7 +25,7 @@ module AddrMon(
                          (dcount == 2'b10) ? periods[2] :
                                              periods[3]) };
 
-       always @ (negedge clk) begin
+       always @ (posedge clk) begin
                if (clkdv == 31) begin
                        clkdv <= 0;
                        dcount <= dcount + 1;
index 1450b2c..fcc396b 100644 (file)
@@ -34,7 +34,7 @@ module Interrupt(
                       imasked[3] ? 8'h58 :
                       imasked[4] ? 8'h60 : 8'h00;
 
-       always @(negedge clk)
+       always @(posedge clk)
        begin
                if (wr && (addr == `ADDR_IF || addr == `ADDR_IE)) begin
                        case(addr)
index 41abaa5..21b1dec 100644 (file)
--- a/Sound1.v
+++ b/Sound1.v
@@ -34,7 +34,7 @@ module Sound1(
                         addr == `ADDR_NR14 ? nr14 : 8'bzzzzzzzz
                      : 8'bzzzzzzzz;
 
-       always @ (negedge core_clk) begin
+       always @ (posedge core_clk) begin
                if(en && wr) begin
                        case(addr)
                        `ADDR_NR10: nr10 <= data;
index 2bb9598..cf8e83a 100644 (file)
--- a/Sound2.v
+++ b/Sound2.v
@@ -32,7 +32,7 @@ module Sound2(
                         addr == `ADDR_NR24 ? nr24 : 8'bzzzzzzzz
                      : 8'bzzzzzzzz;
 
-       always @ (negedge core_clk) begin
+       always @ (posedge core_clk) begin
                if(en && wr) begin
                        case(addr)
                        `ADDR_NR21: nr21 <= data;
index 7752317..626001d 100644 (file)
@@ -36,7 +36,7 @@ module Soundcore(
                         addr == `ADDR_NR52 ? nr52 : 8'bzzzzzzzz
                      : 8'bzzzzzzzz;
 
-       always @ (negedge core_clk) begin
+       always @ (posedge core_clk) begin
                if(wr) begin
                        case(addr)
                        `ADDR_NR50: nr50 <= data;
index 4c5f85b..8f54685 100644 (file)
--- a/System.v
+++ b/System.v
@@ -41,7 +41,7 @@ module MiniRAM(
        reg [7:0] odata;
        assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
        
-       always @(negedge clk)
+       always @(posedge clk)
        begin
                if (decode)     // This has to go this way. The only way XST knows how to do
                begin                           // block ram is chip select, write enable, and always
@@ -65,7 +65,7 @@ module InternalRAM(
        reg [7:0] odata;
        assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
        
-       always @(negedge clk)
+       always @(posedge clk)
        begin
                if (decode)     // This has to go this way. The only way XST knows how to do
                begin                           // block ram is chip select, write enable, and always
@@ -88,7 +88,7 @@ module Switches(
        reg [7:0] odata;
        assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
        
-       always @(negedge clk)
+       always @(posedge clk)
        begin
                if (decode && rd)
                        odata <= switches;
diff --git a/Timer.v b/Timer.v
index 53f392d..e46b38b 100644 (file)
--- a/Timer.v
+++ b/Timer.v
@@ -33,7 +33,7 @@ module Timer(
                        (clkdv[7:0] == 8'b0) :
                     0;
 
-       always @ (negedge clk) 
+       always @ (posedge clk) 
        begin
                if(wr) begin
                        case(addr)
diff --git a/Uart.v b/Uart.v
index 1f0ae7d..f9d71f4 100644 (file)
--- a/Uart.v
+++ b/Uart.v
@@ -25,7 +25,7 @@ module UART(
        
        assign odata = have_data ? 8'b1 : 8'b0;
 
-       always @ (negedge clk)
+       always @ (posedge clk)
        begin
                /* deal with diqing */
                if(newdata) begin
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