`define INSN_LD_reg_imm16 8'b00xx0001
`define INSN_LD_SP_HL 8'b11111001
`define INSN_PUSH_reg 8'b11xx0101
-`define INSN_POP_reg 8'b11xx0001
+`define INSN_POP_reg 8'b11xx0001
+`define INSN_LDH_AC 8'b111x0010 // Either LDH A,(C) or LDH (C),A
+`define INSN_LDx_AHL 8'b001xx010 // LDD/LDI A,(HL) / (HL),A
+`define INSN_ALU8 8'b10xxxxxx // 10 xxx yyy
+`define INSN_NOP 8'b00000000
+`define INSN_RST 8'b11xxx111
+`define INSN_RET 8'b110x1001 // 1 = RETI, 0 = RET
+
`define INSN_reg_A 3'b111
`define INSN_reg_B 3'b000
`define INSN_reg_C 3'b001
`define INSN_stack_BC 2'b00
`define INSN_stack_DE 2'b01
`define INSN_stack_HL 2'b10
+`define INSN_alu_ADD 3'b000
+`define INSN_alu_ADC 3'b001
+`define INSN_alu_SUB 3'b010
+`define INSN_alu_SBC 3'b011
+`define INSN_alu_AND 3'b100
+`define INSN_alu_XOR 3'b101
+`define INSN_alu_OR 3'b110
+`define INSN_alu_CP 3'b111 // Oh lawd, is dat some CP?
+
module GBZ80Core(
input clk,
output reg [15:0] busaddress, /* BUS_* is latched on STATE_FETCH. */
reg [7:0] buswdata;
assign busdata = buswr ? buswdata : 8'bzzzzzzzz;
+ reg ie = 0;
+
initial begin
registers[ 0] <= 0;
registers[ 1] <= 0;
`EXEC_NEXTADDR_PCINC;
rd <= 1;
end
- 1: begin
+ 1: begin
`EXEC_INC_PC;
if (opcode[5:3] == `INSN_reg_dHL) begin
address <= {registers[`REG_H], registers[`REG_L]};
`EXEC_NEWCYCLE;
end
end
- 2: begin
+ 2: begin
`EXEC_NEWCYCLE;
end
endcase
case (cycle)
0: begin
case (opcode[2:0])
- `INSN_reg_A: begin wdata <= registers[`REG_A]; end
- `INSN_reg_B: begin wdata <= registers[`REG_B]; end
- `INSN_reg_C: begin wdata <= registers[`REG_C]; end
- `INSN_reg_D: begin wdata <= registers[`REG_D]; end
- `INSN_reg_E: begin wdata <= registers[`REG_E]; end
- `INSN_reg_H: begin wdata <= registers[`REG_H]; end
- `INSN_reg_L: begin wdata <= registers[`REG_L]; end
+ `INSN_reg_A: wdata <= registers[`REG_A];
+ `INSN_reg_B: wdata <= registers[`REG_B];
+ `INSN_reg_C: wdata <= registers[`REG_C];
+ `INSN_reg_D: wdata <= registers[`REG_D];
+ `INSN_reg_E: wdata <= registers[`REG_E];
+ `INSN_reg_H: wdata <= registers[`REG_H];
+ `INSN_reg_L: wdata <= registers[`REG_L];
endcase
address <= {registers[`REG_H], registers[`REG_L]};
wr <= 1; rd <= 0;
end
`INSN_LD_reg_HL: begin
case(cycle)
- 0: begin
+ 0: begin
address <= {registers[`REG_H], registers[`REG_L]};
rd <= 1;
end
- 1: begin
+ 1: begin
tmp <= rdata;
`EXEC_INC_PC;
`EXEC_NEWCYCLE;
`EXEC_INC_PC;
`EXEC_NEWCYCLE;
case (opcode[2:0])
- `INSN_reg_A: begin tmp <= registers[`REG_A]; end
- `INSN_reg_B: begin tmp <= registers[`REG_B]; end
- `INSN_reg_C: begin tmp <= registers[`REG_C]; end
- `INSN_reg_D: begin tmp <= registers[`REG_D]; end
- `INSN_reg_E: begin tmp <= registers[`REG_E]; end
- `INSN_reg_H: begin tmp <= registers[`REG_H]; end
- `INSN_reg_L: begin tmp <= registers[`REG_L]; end
+ `INSN_reg_A: tmp <= registers[`REG_A];
+ `INSN_reg_B: tmp <= registers[`REG_B];
+ `INSN_reg_C: tmp <= registers[`REG_C];
+ `INSN_reg_D: tmp <= registers[`REG_D];
+ `INSN_reg_E: tmp <= registers[`REG_E];
+ `INSN_reg_H: tmp <= registers[`REG_H];
+ `INSN_reg_L: tmp <= registers[`REG_L];
endcase
end
`INSN_LD_reg_imm16: begin
end
`INSN_PUSH_reg: begin /* PUSH is 16 cycles! */
case (cycle)
- 0: begin
+ 0: begin
wr <= 1;
address <= {registers[`REG_SPH],registers[`REG_SPL]}-1;
case (opcode[5:4])
`INSN_stack_HL: wdata <= registers[`REG_H];
endcase
end
- 1: begin
+ 1: begin
wr <= 1;
address <= {registers[`REG_SPH],registers[`REG_SPL]}-1;
case (opcode[5:4])
endcase
end
2: begin /* TWIDDLE OUR FUCKING THUMBS! */ end
- 3: begin
+ 3: begin
`EXEC_NEWCYCLE;
`EXEC_INC_PC;
end
end
`INSN_POP_reg: begin /* POP is 12 cycles! */
case (cycle)
- 0: begin
+ 0: begin
rd <= 1;
address <= {registers[`REG_SPH],registers[`REG_SPL]};
end
- 1: begin
+ 1: begin
rd <= 1;
address <= {registers[`REG_SPH],registers[`REG_SPL]};
end
- 2: begin
+ 2: begin
+ `EXEC_NEWCYCLE;
+ `EXEC_INC_PC;
+ end
+ endcase
+ end
+ `INSN_LDH_AC: begin
+ case (cycle)
+ 0: begin
+ address <= {8'hFF,registers[`REG_C]};
+ if (opcode[4]) begin // LD A,(C)
+ rd <= 1;
+ end else begin
+ wr <= 1;
+ wdata <= registers[`REG_A];
+ end
+ end
+ 1: begin
+ `EXEC_NEWCYCLE;
+ `EXEC_INC_PC;
+ end
+ endcase
+ end
+ `INSN_LDx_AHL: begin
+ case (cycle)
+ 0: begin
+ address <= {registers[`REG_H],registers[`REG_L]};
+ if (opcode[3]) begin // LDx A, (HL)
+ rd <= 1;
+ end else begin
+ wr <= 1;
+ wdata <= registers[`REG_A];
+ end
+ end
+ 1: begin
`EXEC_NEWCYCLE;
`EXEC_INC_PC;
end
endcase
end
+ `INSN_ALU8: begin
+ if ((opcode[2:0] == `INSN_reg_dHL) && (cycle == 0)) begin
+ // fffffffff fuck your shit, read from (HL) :(
+ rd <= 1;
+ address <= {registers[`REG_H], registers[`REG_L]};
+ end else begin
+ `EXEC_NEWCYCLE;
+ `EXEC_INC_PC;
+ case (opcode[2:0])
+ `INSN_reg_A: tmp <= registers[`REG_A];
+ `INSN_reg_B: tmp <= registers[`REG_B];
+ `INSN_reg_C: tmp <= registers[`REG_C];
+ `INSN_reg_D: tmp <= registers[`REG_D];
+ `INSN_reg_E: tmp <= registers[`REG_E];
+ `INSN_reg_H: tmp <= registers[`REG_H];
+ `INSN_reg_L: tmp <= registers[`REG_L];
+ `INSN_reg_dHL: tmp <= rdata;
+ endcase
+ end
+ end
+ `INSN_NOP: begin
+ `EXEC_NEWCYCLE;
+ `EXEC_INC_PC;
+ end
+ `INSN_RST: begin
+ case (cycle)
+ 0: begin
+ `EXEC_INC_PC; // This goes FIRST in RST
+ end
+ 1: begin
+ wr <= 1;
+ address <= {registers[`REG_SPH],registers[`REG_SPL]}-1;
+ wdata <= registers[`REG_PCH];
+ end
+ 2: begin
+ wr <= 1;
+ address <= {registers[`REG_SPH],registers[`REG_SPL]}-2;
+ wdata <= registers[`REG_PCL];
+ end
+ 3: begin
+ `EXEC_NEWCYCLE;
+ {registers[`REG_PCH],registers[`REG_PCL]} <=
+ {10'b0,opcode[5:3],3'b0};
+ end
+ endcase
+ end
+ `INSN_RET: begin
+ case (cycle)
+ 0: begin
+ rd <= 1;
+ address <= {registers[`REG_SPH],registers[`REG_SPL]};
+ end
+ 1: begin
+ rd <= 1;
+ address <= {registers[`REG_SPH],registers[`REG_SPL]} + 1;
+ end
+ 2: begin /* twiddle thumbs */ end
+ 3: begin
+ `EXEC_NEWCYCLE;
+ // do NOT increment PC!
+ end
+ endcase
+ end
default:
$stop;
endcase
casex (opcode)
`INSN_LD_reg_imm8:
case (cycle)
- 0: cycle <= 1;
- 1: case (opcode[5:3])
+ 0: cycle <= 1;
+ 1: case (opcode[5:3])
`INSN_reg_A: begin registers[`REG_A] <= rdata; cycle <= 0; end
`INSN_reg_B: begin registers[`REG_B] <= rdata; cycle <= 0; end
`INSN_reg_C: begin registers[`REG_C] <= rdata; cycle <= 0; end
`INSN_reg_L: begin registers[`REG_L] <= rdata; cycle <= 0; end
`INSN_reg_dHL: cycle <= 2;
endcase
- 2: cycle <= 0;
+ 2: cycle <= 0;
endcase
`INSN_HALT: begin
/* Nothing needs happen here. */
end
`INSN_LD_HL_reg: begin
case (cycle)
- 0: cycle <= 1;
- 1: cycle <= 0;
+ 0: cycle <= 1;
+ 1: cycle <= 0;
endcase
end
`INSN_LD_reg_HL: begin
0: cycle <= 1;
1: begin
case (opcode[5:3])
- `INSN_reg_A: begin registers[`REG_A] <= tmp; end
- `INSN_reg_B: begin registers[`REG_B] <= tmp; end
- `INSN_reg_C: begin registers[`REG_C] <= tmp; end
- `INSN_reg_D: begin registers[`REG_D] <= tmp; end
- `INSN_reg_E: begin registers[`REG_E] <= tmp; end
- `INSN_reg_H: begin registers[`REG_H] <= tmp; end
- `INSN_reg_L: begin registers[`REG_L] <= tmp; end
+ `INSN_reg_A: registers[`REG_A] <= tmp;
+ `INSN_reg_B: registers[`REG_B] <= tmp;
+ `INSN_reg_C: registers[`REG_C] <= tmp;
+ `INSN_reg_D: registers[`REG_D] <= tmp;
+ `INSN_reg_E: registers[`REG_E] <= tmp;
+ `INSN_reg_H: registers[`REG_H] <= tmp;
+ `INSN_reg_L: registers[`REG_L] <= tmp;
endcase
cycle <= 0;
end
end
`INSN_LD_reg_reg: begin
case (opcode[5:3])
- `INSN_reg_A: begin registers[`REG_A] <= tmp; end
- `INSN_reg_B: begin registers[`REG_B] <= tmp; end
- `INSN_reg_C: begin registers[`REG_C] <= tmp; end
- `INSN_reg_D: begin registers[`REG_D] <= tmp; end
- `INSN_reg_E: begin registers[`REG_E] <= tmp; end
- `INSN_reg_H: begin registers[`REG_H] <= tmp; end
- `INSN_reg_L: begin registers[`REG_L] <= tmp; end
+ `INSN_reg_A: registers[`REG_A] <= tmp;
+ `INSN_reg_B: registers[`REG_B] <= tmp;
+ `INSN_reg_C: registers[`REG_C] <= tmp;
+ `INSN_reg_D: registers[`REG_D] <= tmp;
+ `INSN_reg_E: registers[`REG_E] <= tmp;
+ `INSN_reg_H: registers[`REG_H] <= tmp;
+ `INSN_reg_L: registers[`REG_L] <= tmp;
endcase
end
`INSN_LD_reg_imm16: begin
cycle <= 0;
end
endcase
- end
+ end
+ `INSN_LDH_AC: begin
+ case (cycle)
+ 0: cycle <= 1;
+ 1: begin
+ cycle <= 0;
+ if (opcode[4])
+ registers[`REG_A] <= rdata;
+ end
+ endcase
+ end
+ `INSN_LDx_AHL: begin
+ case (cycle)
+ 0: cycle <= 1;
+ 1: begin
+ cycle <= 0;
+ if (opcode[3])
+ registers[`REG_A] <= rdata;
+ {registers[`REG_H],registers[`REG_L]} <=
+ opcode[4] ? // if set, LDD, else LDI
+ ({registers[`REG_H],registers[`REG_L]} - 1) :
+ ({registers[`REG_H],registers[`REG_L]} + 1);
+ end
+ endcase
+ end
+ `INSN_ALU8: begin
+ if ((opcode[2:0] == `INSN_reg_dHL) && (cycle == 0)) begin
+ /* Sit on our asses. */
+ cycle <= 1;
+ end else begin /* Actually do the computation! */
+ case (opcode[5:3])
+ `INSN_alu_ADD: begin
+ registers[`REG_A] <=
+ registers[`REG_A] + tmp;
+ registers[`REG_F] <=
+ { /* Z */ ((registers[`REG_A] + tmp) == 0) ? 1'b1 : 1'b0,
+ /* N */ 1'b0,
+ /* H */ (({1'b0,registers[`REG_A][3:0]} + {1'b0,tmp[3:0]}) >> 4 == 1) ? 1'b1 : 1'b0,
+ /* C */ (({1'b0,registers[`REG_A]} + {1'b0,tmp}) >> 8 == 1) ? 1'b1 : 1'b0,
+ registers[`REG_F][3:0]
+ };
+ end
+ `INSN_alu_ADC: begin
+ registers[`REG_A] <=
+ registers[`REG_A] + tmp + {7'b0,registers[`REG_F][4]};
+ registers[`REG_F] <=
+ { /* Z */ ((registers[`REG_A] + tmp + {7'b0,registers[`REG_F][4]}) == 0) ? 1'b1 : 1'b0,
+ /* N */ 1'b0,
+ /* H */ (({1'b0,registers[`REG_A][3:0]} + {1'b0,tmp[3:0]} + {4'b0,registers[`REG_F][4]}) >> 4 == 1) ? 1'b1 : 1'b0,
+ /* C */ (({1'b0,registers[`REG_A]} + {1'b0,tmp} + {8'b0,registers[`REG_F][4]}) >> 8 == 1) ? 1'b1 : 1'b0,
+ registers[`REG_F][3:0]
+ };
+ end
+ `INSN_alu_AND: begin
+ registers[`REG_A] <=
+ registers[`REG_A] & tmp;
+ registers[`REG_F] <=
+ { /* Z */ ((registers[`REG_A] & tmp) == 0) ? 1'b1 : 1'b0,
+ 3'b010,
+ registers[`REG_F][3:0]
+ };
+ end
+ `INSN_alu_OR: begin
+ registers[`REG_A] <=
+ registers[`REG_A] | tmp;
+ registers[`REG_F] <=
+ { /* Z */ ((registers[`REG_A] | tmp) == 0) ? 1'b1 : 1'b0,
+ 3'b000,
+ registers[`REG_F][3:0]
+ };
+ end
+ `INSN_alu_XOR: begin
+ registers[`REG_A] <=
+ registers[`REG_A] ^ tmp;
+ registers[`REG_F] <=
+ { /* Z */ ((registers[`REG_A] ^ tmp) == 0) ? 1'b1 : 1'b0,
+ 3'b000,
+ registers[`REG_F][3:0]
+ };
+ end
+ default:
+ $stop;
+ endcase
+ end
+ end
+ `INSN_NOP: begin /* NOP! */ end
+ `INSN_RST: begin
+ case (cycle)
+ 0: cycle <= 1;
+ 1: cycle <= 2;
+ 2: cycle <= 3;
+ 3: begin
+ cycle <= 0;
+ {registers[`REG_SPH],registers[`REG_SPL]} <=
+ {registers[`REG_SPH],registers[`REG_SPL]}-2;
+ end
+ endcase
+ end
+ `INSN_RET: begin
+ case (cycle)
+ 0: cycle <= 1;
+ 1: begin
+ cycle <= 2;
+ registers[`REG_PCL] <= rdata;
+ end
+ 2: begin
+ cycle <= 3;
+ registers[`REG_PCH] <= rdata;
+ end
+ 3: begin
+ cycle <= 0;
+ {registers[`REG_SPH],registers[`REG_SPL]} <=
+ {registers[`REG_SPH],registers[`REG_SPL]} + 2;
+ if (opcode[4]) /* RETI */
+ ie <= 1;
+ end
+ endcase
+ end
endcase
state <= `STATE_FETCH;
end
git.joshuawise.com / fpgaboy.git / blobdiff