`timescale 1ns / 1ps module SimROM( input [15:0] address, inout [7:0] data, input clk, input wr, rd); reg rdlatch = 0; reg [7:0] odata; reg [7:0] rom [32767:0]; initial $readmemh("rom.hex", rom); wire decode = address[15:13] == 0; always @(posedge clk) begin rdlatch <= rd && decode; odata <= rom[address[10:0]]; end assign data = rdlatch ? odata : 8'bzzzzzzzz; endmodule module BootstrapROM( input [15:0] address, inout [7:0] data, input clk, input wr, rd); reg rdlatch = 0; reg [7:0] addrlatch = 0; reg romno = 0, romnotmp = 0; reg [7:0] brom0 [255:0]; reg [7:0] brom1 [255:0]; initial $readmemh("fpgaboot.hex", brom0); initial $readmemh("gbboot.hex", brom1); `ifdef isim initial romno <= 1; `endif wire decode = address[15:8] == 0; wire [7:0] odata = (romno == 0) ? brom0[addrlatch] : brom1[addrlatch]; always @(posedge clk) begin rdlatch <= rd && decode; addrlatch <= address[7:0]; if (wr && decode) romnotmp <= data[0]; if (rd && address == 16'h0000) romno <= romnotmp; /* Latch when the program restarts. */ end assign data = rdlatch ? odata : 8'bzzzzzzzz; endmodule module MiniRAM( input [15:0] address, inout [7:0] data, input clk, input wr, rd); reg [7:0] ram [127:0]; wire decode = (address >= 16'hFF80) && (address <= 16'hFFFE); reg rdlatch = 0; reg [7:0] odata; assign data = rdlatch ? odata : 8'bzzzzzzzz; always @(posedge clk) begin rdlatch <= rd && decode; if (decode) // This has to go this way. The only way XST knows how to do begin // block ram is chip select, write enable, and always if (wr) // reading. "else if rd" does not cut it ... ram[address[6:0]] <= data; odata <= ram[address[6:0]]; end end endmodule module CellularRAM( input clk, input [15:0] address, inout [7:0] data, input wr, rd, output wire cr_nADV, cr_nCE, cr_nOE, cr_nWE, cr_CRE, cr_nLB, cr_nUB, cr_CLK, output wire st_nCE, st_nRST, output wire [22:0] cr_A, inout [15:0] cr_DQ); parameter ADDR_PROGADDRH = 16'hFF60; parameter ADDR_PROGADDRM = 16'hFF61; parameter ADDR_PROGADDRL = 16'hFF62; parameter ADDR_PROGDATA = 16'hFF63; parameter ADDR_PROGFLASH = 16'hFF65; parameter ADDR_MBC = 16'hFF64; reg rdlatch = 0, wrlatch = 0; reg [15:0] addrlatch = 0; reg [7:0] datalatch = 0; reg [7:0] progaddrh, progaddrm, progaddrl; reg [22:0] progaddr; reg [7:0] mbc_emul = 8'b00000101; // High bit is whether we're poking flash // low 7 bits are the MBC that we are emulating assign cr_nADV = 0; /* Addresses are always valid! :D */ assign cr_nCE = ~(addrlatch != ADDR_PROGFLASH); /* The chip is enabled */ assign cr_nLB = 0; /* Lower byte is enabled */ assign cr_nUB = 0; /* Upper byte is enabled */ assign cr_CRE = 0; /* Data writes, not config */ assign cr_CLK = 0; /* Clock? I think not! */ assign st_nRST = 1; /* Keep the strataflash out of reset. */ assign st_nCE = ~(addrlatch == ADDR_PROGFLASH); wire decode = (addrlatch[15:14] == 2'b00) /* extrom */ || (addrlatch[15:13] == 3'b101) /* extram */ || (addrlatch == ADDR_PROGDATA) || (addrlatch == ADDR_PROGFLASH); reg [3:0] rambank = 0; reg [8:0] rombank = 1; assign cr_nOE = decode ? ~rdlatch : 1; assign cr_nWE = (decode && ((addrlatch == ADDR_PROGDATA) || (addrlatch == ADDR_PROGFLASH) || (mbc_emul[6:0] == 0) || (addrlatch[15:13] == 3'b101))) ? ~wrlatch : 1; assign cr_DQ = (~cr_nOE) ? 16'bzzzzzzzzzzzzzzzz : {8'b0, datalatch}; assign cr_A = (addrlatch[15:14] == 2'b00) ? /* extrom, home bank */ {9'b0,addrlatch[13:0]} : (addrlatch[15:14] == 2'b01) ? /* extrom, paged bank */ {rombank, addrlatch[13:0]} : (addrlatch[15:13] == 3'b101) ? /* extram */ {1'b1, 5'b0, rambank, addrlatch[12:0]} : ((addrlatch == ADDR_PROGDATA) || (addrlatch == ADDR_PROGFLASH)) ? progaddr : 23'b0; always @(posedge clk) begin case (address) ADDR_PROGADDRH: if (wr) progaddrh <= data; ADDR_PROGADDRM: if (wr) progaddrm <= data; ADDR_PROGADDRL: if (wr) progaddrl <= data; ADDR_PROGDATA: if (rd || wr) begin progaddr <= {progaddrh[6:0], progaddrm[7:0], progaddrl[7:0]}; {progaddrh[6:0], progaddrm[7:0], progaddrl[7:0]} <= {progaddrh[6:0], progaddrm[7:0], progaddrl[7:0]} + 23'b1; end ADDR_MBC: begin mbc_emul <= data; rambank <= 0; rombank <= 1; end endcase if (mbc_emul[6:0] == 5) begin if ((address[15:12] == 4'h2) && wr) rombank <= {rombank[8], data}; else if ((address[15:12] == 4'h3) && wr) rombank <= {data[0], rombank[7:0]}; else if ((address[15:12] == 4'h4) && wr) rambank <= data[3:0]; end rdlatch <= rd; wrlatch <= wr; addrlatch <= address; datalatch <= data; end assign data = (rdlatch && decode) ? (addrlatch == ADDR_PROGADDRH) ? progaddrh : (addrlatch == ADDR_PROGADDRM) ? progaddrm : (addrlatch == ADDR_PROGADDRL) ? progaddrl : cr_DQ : 8'bzzzzzzzz; endmodule module InternalRAM( input [15:0] address, inout [7:0] data, input clk, input wr, rd); // synthesis attribute ram_style of ram is block reg [7:0] ram [8191:0]; wire decode = (address >= 16'hC000) && (address <= 16'hFDFF); /* This includes echo RAM. */ reg [7:0] odata; reg rdlatch = 0; assign data = rdlatch ? odata : 8'bzzzzzzzz; always @(posedge clk) begin rdlatch <= rd && decode; if (decode) // This has to go this way. The only way XST knows how to do begin // block ram is chip select, write enable, and always if (wr) // reading. "else if rd" does not cut it ... ram[address[12:0]] <= data; odata <= ram[address[12:0]]; end end endmodule module Switches( input [15:0] address, inout [7:0] data, input clk, input wr, rd, input [7:0] switches, output reg [7:0] ledout = 0); wire decode = address == 16'hFF51; reg [7:0] odata; reg rdlatch = 0; assign data = rdlatch ? odata : 8'bzzzzzzzz; always @(posedge clk) begin rdlatch <= rd && decode; if (decode && rd) odata <= switches; else if (decode && wr) ledout <= data; end endmodule `ifdef isim module Dumpable(input [2:0] r, g, input [1:0] b, input hs, vs, vgaclk); endmodule `endif module CoreTop( `ifdef isim output reg vgaclk = 0, output reg clk = 0, `else input xtal, input [7:0] switches, input [3:0] buttons, output wire [7:0] leds, output serio, input serin, output wire [3:0] digits, output wire [7:0] seven, output wire cr_nADV, cr_nCE, cr_nOE, cr_nWE, cr_CRE, cr_nLB, cr_nUB, cr_CLK, st_nCE, st_nRST, output wire [22:0] cr_A, inout [15:0] cr_DQ, input ps2c, ps2d, `endif output wire hs, vs, output wire [2:0] r, g, output wire [1:0] b, output wire soundl, soundr); `ifdef isim always #62 clk <= ~clk; always #100 vgaclk <= ~vgaclk; Dumpable dump(r,g,b,hs,vs,vgaclk); wire [7:0] leds; wire serio; wire serin = 1; wire [3:0] digits; wire [7:0] seven; wire [7:0] switches = 8'b0; wire [3:0] buttons = 4'b0; `else wire xtalb, clk, vgaclk; IBUFG iclkbuf(.O(xtalb), .I(xtal)); CPUDCM dcm (.CLKIN_IN(xtalb), .CLKFX_OUT(clk)); pixDCM pixdcm (.CLKIN_IN(xtalb), .CLKFX_OUT(vgaclk)); wire [7:0] ps2buttons; `endif wire [15:0] addr [1:0]; wire [7:0] data [1:0]; wire wr [1:0], rd [1:0]; wire irq, tmrirq, lcdcirq, vblankirq, btnirq; wire [7:0] jaddr; wire [1:0] state; wire ack; GBZ80Core core( .clk(clk), .bus0address(addr[0]), .bus0data(data[0]), .bus0wr(wr[0]), .bus0rd(rd[0]), .bus1address(addr[1]), .bus1data(data[1]), .bus1wr(wr[1]), .bus1rd(rd[1]), .irq(irq), .irqack(ack), .jaddr(jaddr), .state(state)); BootstrapROM brom( .address(addr[1]), .data(data[1]), .clk(clk), .wr(wr[1]), .rd(rd[1])); `ifdef isim SimROM rom( .address(addr[0]), .data(data[0]), .clk(clk), .wr(wr[0]), .rd(rd[0])); `else CellularRAM cellram( .address(addr[0]), .data(data[0]), .clk(clk), .wr(wr[0]), .rd(rd[0]), .cr_nADV(cr_nADV), .cr_nCE(cr_nCE), .cr_nOE(cr_nOE), .cr_nWE(cr_nWE), .cr_CRE(cr_CRE), .cr_nLB(cr_nLB), .cr_nUB(cr_nUB), .cr_CLK(cr_CLK), .cr_A(cr_A), .cr_DQ(cr_DQ), .st_nCE(st_nCE), .st_nRST(st_nRST)); `endif wire lcdhs, lcdvs, lcdclk; wire [2:0] lcdr, lcdg; wire [1:0] lcdb; LCDC lcdc( .clk(clk), .addr(addr[0]), .data(data[0]), .wr(wr[0]), .rd(rd[0]), .lcdcirq(lcdcirq), .vblankirq(vblankirq), .lcdclk(lcdclk), .lcdhs(lcdhs), .lcdvs(lcdvs), .lcdr(lcdr), .lcdg(lcdg), .lcdb(lcdb)); Framebuffer fb( .lcdclk(lcdclk), .lcdhs(lcdhs), .lcdvs(lcdvs), .lcdr(lcdr), .lcdg(lcdg), .lcdb(lcdb), .vgaclk(vgaclk), .vgahs(hs), .vgavs(vs), .vgar(r), .vgag(g), .vgab(b)); wire [7:0] sleds; `ifdef isim assign leds = sleds; `else assign leds = sleds | ps2buttons; `endif Switches sw( .clk(clk), .address(addr[0]), .data(data[0]), .wr(wr[0]), .rd(rd[0]), .ledout(sleds), .switches(switches) ); `ifdef isim `else PS2Button ps2( .clk(clk), .inclk(ps2c), .indata(ps2d), .buttons(ps2buttons) ); `endif Buttons ass( .core_clk(clk), .addr(addr[0]), .data(data[0]), .wr(wr[0]), .rd(rd[0]), .int(btnirq), `ifdef isim .buttons(switches) `else .buttons(ps2buttons) `endif ); AddrMon amon( .clk(clk), .addr(addr[0]), .digit(digits), .out(seven), .freeze(buttons[0]), .periods( (state == 2'b00) ? 4'b0010 : (state == 2'b01) ? 4'b0001 : (state == 2'b10) ? 4'b1000 : 4'b0100) ); UART nouart ( /* no u */ .clk(clk), .addr(addr[0]), .data(data[0]), .wr(wr[0]), .rd(rd[0]), .serial(serio), .serialrx(serin) ); InternalRAM ram( .clk(clk), .address(addr[0]), .data(data[0]), .wr(wr[0]), .rd(rd[0]) ); MiniRAM mram( .clk(clk), .address(addr[1]), .data(data[1]), .wr(wr[1]), .rd(rd[1]) ); Timer tmr( .clk(clk), .addr(addr[0]), .data(data[0]), .wr(wr[0]), .rd(rd[0]), .irq(tmrirq) ); Interrupt intr( .clk(clk), .addr(addr[0]), .data(data[0]), .wr(wr[0]), .rd(rd[0]), .vblank(vblankirq), .lcdc(lcdcirq), .tovf(tmrirq), .serial(1'b0), .buttons(btnirq), .master(irq), .ack(ack), .jaddr(jaddr)); Soundcore sound( .core_clk(clk), .addr(addr[0]), .data(data[0]), .rd(rd[0]), .wr(wr[0]), .snd_data_l(soundl), .snd_data_r(soundr)); endmodule