Add set/res, which fixes some crashes in the test suite
[fpgaboy.git] / core / insn_setres.v
1 `define INSN_SETRES             9'b11xxxxxxx
2
3 `ifdef EXECUTE
4         `INSN_SETRES: begin
5                 if ((opcode[2:0] == `INSN_reg_dHL) && (cycle == 0)) begin
6                         `EXEC_READ(`_HL)
7                 end else if ((opcode[2:0] == `INSN_reg_dHL) && (cycle == 3)) begin
8                         `EXEC_NEWCYCLE
9                 end else begin  /* It doesn't hurt for this to be done on cycle = 3, but it doesn't do any good then either. */
10                         `EXEC_INC_PC
11                         case (opcode[2:0])
12                         `INSN_reg_A:    tmp <= opcode[6] ? (`_A | (8'b1 << opcode[5:3])) : (`_A & ~(8'b1 << opcode[5:3]));
13                         `INSN_reg_B:    tmp <= opcode[6] ? (`_B | (8'b1 << opcode[5:3])) : (`_B & ~(8'b1 << opcode[5:3]));
14                         `INSN_reg_C:    tmp <= opcode[6] ? (`_C | (8'b1 << opcode[5:3])) : (`_C & ~(8'b1 << opcode[5:3]));
15                         `INSN_reg_D:    tmp <= opcode[6] ? (`_D | (8'b1 << opcode[5:3])) : (`_D & ~(8'b1 << opcode[5:3]));
16                         `INSN_reg_E:    tmp <= opcode[6] ? (`_E | (8'b1 << opcode[5:3])) : (`_E & ~(8'b1 << opcode[5:3]));
17                         `INSN_reg_H:    tmp <= opcode[6] ? (`_H | (8'b1 << opcode[5:3])) : (`_H & ~(8'b1 << opcode[5:3]));
18                         `INSN_reg_L:    tmp <= opcode[6] ? (`_L | (8'b1 << opcode[5:3])) : (`_L & ~(8'b1 << opcode[5:3]));
19                         `INSN_reg_dHL:  tmp <= opcode[6] ? (rdata | (8'b1 << opcode[5:3])) : (rdata & ~(8'b1 << opcode[5:3]));
20                         endcase
21                         if (opcode[2:0] != `INSN_reg_dHL) begin
22                                 `EXEC_NEWCYCLE
23                         end
24                 end
25         end
26 `endif
27
28 `ifdef WRITEBACK
29         `INSN_SETRES: begin
30                 if ((opcode[2:0] != `INSN_reg_dHL) || (cycle == 1))
31                         case (opcode[2:0])
32                         `INSN_reg_A:    `_A <= tmp;
33                         `INSN_reg_B:    `_B <= tmp;
34                         `INSN_reg_C:    `_C <= tmp;
35                         `INSN_reg_D:    `_D <= tmp;
36                         `INSN_reg_E:    `_E <= tmp;
37                         `INSN_reg_H:    `_H <= tmp;
38                         `INSN_reg_L:    `_L <= tmp;
39                         `INSN_reg_dHL:  begin `EXEC_WRITE(`_HL, tmp) end
40                         endcase
41         end
42 `endif
This page took 0.023991 seconds and 4 git commands to generate.