`define INSN_SETRES 9'b11xxxxxxx `ifdef EXECUTE `INSN_SETRES: begin if ((opcode[2:0] == `INSN_reg_dHL) && (cycle == 0)) begin `EXEC_READ(`_HL) end else if ((opcode[2:0] == `INSN_reg_dHL) && (cycle == 3)) begin `EXEC_NEWCYCLE end else begin /* It doesn't hurt for this to be done on cycle = 3, but it doesn't do any good then either. */ `EXEC_INC_PC case (opcode[2:0]) `INSN_reg_A: tmp <= opcode[6] ? (`_A | (8'b1 << opcode[5:3])) : (`_A & ~(8'b1 << opcode[5:3])); `INSN_reg_B: tmp <= opcode[6] ? (`_B | (8'b1 << opcode[5:3])) : (`_B & ~(8'b1 << opcode[5:3])); `INSN_reg_C: tmp <= opcode[6] ? (`_C | (8'b1 << opcode[5:3])) : (`_C & ~(8'b1 << opcode[5:3])); `INSN_reg_D: tmp <= opcode[6] ? (`_D | (8'b1 << opcode[5:3])) : (`_D & ~(8'b1 << opcode[5:3])); `INSN_reg_E: tmp <= opcode[6] ? (`_E | (8'b1 << opcode[5:3])) : (`_E & ~(8'b1 << opcode[5:3])); `INSN_reg_H: tmp <= opcode[6] ? (`_H | (8'b1 << opcode[5:3])) : (`_H & ~(8'b1 << opcode[5:3])); `INSN_reg_L: tmp <= opcode[6] ? (`_L | (8'b1 << opcode[5:3])) : (`_L & ~(8'b1 << opcode[5:3])); `INSN_reg_dHL: tmp <= opcode[6] ? (rdata | (8'b1 << opcode[5:3])) : (rdata & ~(8'b1 << opcode[5:3])); endcase if (opcode[2:0] != `INSN_reg_dHL) begin `EXEC_NEWCYCLE end end end `endif `ifdef WRITEBACK `INSN_SETRES: begin if ((opcode[2:0] != `INSN_reg_dHL) || (cycle == 1)) case (opcode[2:0]) `INSN_reg_A: `_A <= tmp; `INSN_reg_B: `_B <= tmp; `INSN_reg_C: `_C <= tmp; `INSN_reg_D: `_D <= tmp; `INSN_reg_E: `_E <= tmp; `INSN_reg_H: `_H <= tmp; `INSN_reg_L: `_L <= tmp; `INSN_reg_dHL: begin `EXEC_WRITE(`_HL, tmp) end endcase end `endif