core/insn_ld_hl_reg.v

   1 `ifdef EXECUTE
   2         `INSN_LD_HL_reg: begin
   3                 case (cycle)
   4                 0:      begin
   5                                 case (opcode[2:0])
   6                                 `INSN_reg_A:    wdata <= `_A;
   7                                 `INSN_reg_B:    wdata <= `_B;
   8                                 `INSN_reg_C:    wdata <= `_C;
   9                                 `INSN_reg_D:    wdata <= `_D;
  10                                 `INSN_reg_E:    wdata <= `_E;
  11                                 `INSN_reg_H:    wdata <= `_H;
  12                                 `INSN_reg_L:    wdata <= `_L;
  13                                 endcase
  14                                 address <= `_HL;
  15                                 wr <= 1; rd <= 0;
  16                         end
  17                 1:      begin
  18                                 `EXEC_INC_PC
  19                                 `EXEC_NEWCYCLE
  20                         end
  21                 endcase
  22         end
  23 `endif
  24
  25 `ifdef WRITEBACK
  26         `INSN_LD_HL_reg: begin
  27                 /* Nothing of interest here */
  28         end
  29 `endif