[fpgaboy.git] / core / insn_ld_hl_reg.v

`ifdef EXECUTE
	`INSN_LD_HL_reg: begin
		case (cycle)
		0:	begin
				case (opcode[2:0])
				`INSN_reg_A:	wdata <= `_A;
				`INSN_reg_B:	wdata <= `_B;
				`INSN_reg_C:	wdata <= `_C;
				`INSN_reg_D:	wdata <= `_D;
				`INSN_reg_E:	wdata <= `_E;
				`INSN_reg_H:	wdata <= `_H;
				`INSN_reg_L:	wdata <= `_L;
				endcase
				address <= `_HL;
				wr <= 1; rd <= 0;
			end
		1:	begin
				`EXEC_INC_PC
				`EXEC_NEWCYCLE
			end
		endcase
	end
`endif

`ifdef WRITEBACK
	`INSN_LD_HL_reg: begin
		/* Nothing of interest here */
	end
`endif
Commit	Line	Data
81358c71 JW	1	`ifdef EXECUTE
	2	`INSN_LD_HL_reg: begin
	3	case (cycle)
	4	0: begin
	5	case (opcode[2:0])
5c33c5c0 JW	6	`INSN_reg_A: wdata <= `_A;
	7	`INSN_reg_B: wdata <= `_B;
	8	`INSN_reg_C: wdata <= `_C;
	9	`INSN_reg_D: wdata <= `_D;
	10	`INSN_reg_E: wdata <= `_E;
	11	`INSN_reg_H: wdata <= `_H;
	12	`INSN_reg_L: wdata <= `_L;
81358c71	13	endcase
5c33c5c0	14	address <= `_HL;
81358c71 JW	15	wr <= 1; rd <= 0;
	16	end
	17	1: begin
5c33c5c0 JW	18	`EXEC_INC_PC
5c33c5c0 JW	19	`EXEC_NEWCYCLE
81358c71 JW	20	end
	21	endcase
	22	end
	23	`endif
	24
	25	`ifdef WRITEBACK
	26	`INSN_LD_HL_reg: begin
	27	/* Nothing of interest here */
	28	end
	29	`endif