]> Joshua Wise's Git repositories - fpgaboy.git/blob - core/insn_jp-jpcc.v
Merge branch 'master' of lu@anyus.res.cmu.edu:/storage/fpga/FPGABoy
[fpgaboy.git] / core / insn_jp-jpcc.v
1 `define INSN_JP_imm             9'b011000011
2 `define INSN_JPCC_imm           9'b0110xx010
3
4 `ifdef EXECUTE
5         `INSN_JP_imm,`INSN_JPCC_imm: begin
6                 case (cycle)
7                 0:      begin
8                                 `EXEC_INC_PC
9                                 `EXEC_READ(`_PC + 1)
10                         end
11                 1:      begin
12                                 `EXEC_INC_PC
13                                 `EXEC_READ(`_PC + 1)
14                         end
15                 2:      begin
16                                 `EXEC_INC_PC
17                                 if (!opcode[0]) begin   // i.e., JP cc,nn
18                                         /* We need to check the condition code to bail out. */
19                                         case (opcode[4:3])
20                                         `INSN_cc_NZ:    if (`_F[7]) `EXEC_NEWCYCLE
21                                         `INSN_cc_Z:     if (~`_F[7]) `EXEC_NEWCYCLE
22                                         `INSN_cc_NC:    if (`_F[4]) `EXEC_NEWCYCLE
23                                         `INSN_cc_C:     if (~`_F[4]) `EXEC_NEWCYCLE
24                                         endcase
25                                 end
26                         end
27                 3:      `EXEC_NEWCYCLE
28                 endcase
29         end
30 `endif
31
32 `ifdef WRITEBACK
33         `INSN_JP_imm,`INSN_JPCC_imm: begin
34                 case (cycle)
35                 0:      begin /* type F */ end
36                 1:      tmp <= rdata;   // tmp contains newpcl
37                 2:      tmp2 <= rdata;  // tmp2 contains newpch
38                 3:      `_PC <= {tmp2,tmp};
39                 endcase
40         end
41 `endif
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