Merge branch 'master' of lu@anyus.res.cmu.edu:/storage/fpga/FPGABoy

[fpgaboy.git] / core / insn_jp-jpcc.v

`define INSN_JP_imm		9'b011000011
`define INSN_JPCC_imm		9'b0110xx010

`ifdef EXECUTE
	`INSN_JP_imm,`INSN_JPCC_imm: begin
		case (cycle)
		0:	begin
				`EXEC_INC_PC
				`EXEC_READ(`_PC + 1)
			end
		1:	begin
				`EXEC_INC_PC
				`EXEC_READ(`_PC + 1)
			end
		2:	begin
				`EXEC_INC_PC
				if (!opcode[0]) begin	// i.e., JP cc,nn
					/* We need to check the condition code to bail out. */
					case (opcode[4:3])
					`INSN_cc_NZ:	if (`_F[7]) `EXEC_NEWCYCLE
					`INSN_cc_Z:	if (~`_F[7]) `EXEC_NEWCYCLE
					`INSN_cc_NC:	if (`_F[4]) `EXEC_NEWCYCLE
					`INSN_cc_C:	if (~`_F[4]) `EXEC_NEWCYCLE
					endcase
				end
			end
		3:	`EXEC_NEWCYCLE
		endcase
	end
`endif

`ifdef WRITEBACK
	`INSN_JP_imm,`INSN_JPCC_imm: begin
		case (cycle)
		0:	begin /* type F */ end
		1:	tmp <= rdata;	// tmp contains newpcl
		2:	tmp2 <= rdata;	// tmp2 contains newpch
		3:	`_PC <= {tmp2,tmp};
		endcase
	end
`endif