5 address <= {registers[`REG_H],registers[`REG_L]};
6 if (opcode[3]) begin // LDx A, (HL)
10 wdata <= registers[`REG_A];
24 0: begin /* Type F */ end
27 registers[`REG_A] <= rdata;
28 {registers[`REG_H],registers[`REG_L]} <=
29 opcode[4] ? // if set, LDD, else LDI
30 ({registers[`REG_H],registers[`REG_L]} - 1) :
31 ({registers[`REG_H],registers[`REG_L]} + 1);