]> Joshua Wise's Git repositories - fpgaboy.git/blob - insn_call-callcc.v
Cleanups to make code nicer looking. ALU subtraction fixes.
[fpgaboy.git] / insn_call-callcc.v
1 `ifdef EXECUTE
2         `INSN_CALL,`INSN_CALLCC: begin
3                 case (cycle)
4                 0:      begin
5                                 `EXEC_INC_PC;
6                                 `EXEC_NEXTADDR_PCINC;
7                                 rd <= 1;
8                         end
9                 1:      begin
10                                 `EXEC_INC_PC;
11                                 `EXEC_NEXTADDR_PCINC;
12                                 rd <= 1;
13                         end
14                 2:      begin
15                                 `EXEC_INC_PC;
16                                 if (!opcode[0]) // i.e., is callcc
17                                         /* We need to check the condition code to bail out. */
18                                         case (opcode[4:3])
19                                         `INSN_cc_NZ:    if (registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end
20                                         `INSN_cc_Z:     if (~registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end
21                                         `INSN_cc_NC:    if (registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end
22                                         `INSN_cc_C:     if (~registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end
23                                         endcase
24                         end
25                 3:      begin
26                                 address <= {registers[`REG_SPH],registers[`REG_SPL]} - 1;
27                                 wdata <= registers[`REG_PCH];
28                                 wr <= 1;
29                         end
30                 4:      begin
31                                 address <= {registers[`REG_SPH],registers[`REG_SPL]} - 2;
32                                 wdata <= registers[`REG_PCL];
33                                 wr <= 1;
34                         end
35                 5:      begin
36                                 `EXEC_NEWCYCLE; /* do NOT increment the PC */
37                         end
38                 endcase
39         end
40 `endif
41
42 `ifdef WRITEBACK
43         `INSN_CALL,`INSN_CALLCC: begin
44                 case (cycle)
45                 0:      begin /* type F */ end
46                 1:      tmp <= rdata;   // tmp contains newpcl
47                 2:      tmp2 <= rdata;  // tmp2 contains newpch
48                 3:      begin /* type F */ end
49                 4:      registers[`REG_PCH] <= tmp2;
50                 5: begin
51                                 {registers[`REG_SPH],registers[`REG_SPL]} <=
52                                         {registers[`REG_SPH],registers[`REG_SPL]} - 2;
53                                 registers[`REG_PCL] <= tmp;
54                         end
55                 endcase
56         end
57 `endif
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