12 registers[`REG_A] <= {registers[`REG_A][6:0],registers[`REG_A][7]};
13 registers[`REG_F] <= {registers[`REG_F][7:5],registers[`REG_A][7],registers[`REG_F][3:0]};
16 registers[`REG_A] <= {registers[`REG_A][0],registers[`REG_A][7:1]};
17 registers[`REG_F] <= {registers[`REG_F][7:5],registers[`REG_A][0],registers[`REG_F][3:0]};
20 registers[`REG_A] <= {registers[`REG_A][6:0],registers[`REG_F][4]};
21 registers[`REG_F] <= {registers[`REG_F][7:5],registers[`REG_A][7],registers[`REG_F][3:0]};
24 registers[`REG_A] <= {registers[`REG_A][4],registers[`REG_A][7:1]};
25 registers[`REG_F] <= {registers[`REG_F][7:5],registers[`REG_A][0],registers[`REG_F][3:0]};
28 registers[`REG_A] <= ~registers[`REG_A];
29 registers[`REG_F] <= {registers[`REG_F][7],1'b1,1'b1,registers[`REG_F][4:0]};
32 registers[`REG_F] <= {registers[`REG_F][7:5],1'b1,registers[`REG_F][3:0]};
35 registers[`REG_F] <= {registers[`REG_F][7:5],~registers[`REG_F][4],registers[`REG_F][3:0]};