Split out more insns

[fpgaboy.git] / insn_alu_a.v

`ifdef EXECUTE
	`INSN_ALU_A: begin
		`EXEC_NEWCYCLE;
		`EXEC_INC_PC;
	end
`endif

`ifdef WRITEBACK
	`INSN_ALU_A: begin
		case(opcode[5:3])
		`INSN_alu_RLCA: begin
			registers[`REG_A] <= {registers[`REG_A][6:0],registers[`REG_A][7]};
			registers[`REG_F] <= {registers[`REG_F][7:5],registers[`REG_A][7],registers[`REG_F][3:0]};
		end
		`INSN_alu_RRCA: begin
			registers[`REG_A] <= {registers[`REG_A][0],registers[`REG_A][7:1]};
			registers[`REG_F] <= {registers[`REG_F][7:5],registers[`REG_A][0],registers[`REG_F][3:0]};
		end
		`INSN_alu_RLA: begin
			registers[`REG_A] <= {registers[`REG_A][6:0],registers[`REG_F][4]};
			registers[`REG_F] <= {registers[`REG_F][7:5],registers[`REG_A][7],registers[`REG_F][3:0]};
		end
		`INSN_alu_RRA: begin
			registers[`REG_A] <= {registers[`REG_A][4],registers[`REG_A][7:1]};
			registers[`REG_F] <= {registers[`REG_F][7:5],registers[`REG_A][0],registers[`REG_F][3:0]};
		end
		`INSN_alu_CPL: begin
			registers[`REG_A] <= ~registers[`REG_A];
			registers[`REG_F] <= {registers[`REG_F][7],1'b1,1'b1,registers[`REG_F][4:0]};
		end
		`INSN_alu_SCF: begin
			registers[`REG_F] <= {registers[`REG_F][7:5],1'b1,registers[`REG_F][3:0]};
		end
		`INSN_alu_CCF: begin
			registers[`REG_F] <= {registers[`REG_F][7:5],~registers[`REG_F][4],registers[`REG_F][3:0]};
		end
		endcase
	end
`endif