Merge branch 'master' of andrew:/afs/andrew/usr/czl/public/FPGABoy

[fpgaboy.git] / core / insn_alu_a.v

`define INSN_alu_RLCA		3'b000
`define INSN_alu_RRCA		3'b001
`define INSN_alu_RLA		3'b010
`define INSN_alu_RRA		3'b011
`define INSN_alu_DAA		3'b100
`define INSN_alu_CPL		3'b101
`define INSN_alu_SCF		3'b110
`define INSN_alu_CCF		3'b111

`define INSN_ALU_A		9'b000xxx111

`ifdef EXECUTE
	`INSN_ALU_A: begin
		`EXEC_NEWCYCLE
		`EXEC_INC_PC
	end
`endif

`ifdef WRITEBACK
	`INSN_ALU_A: begin
		case(opcode[5:3])
		`INSN_alu_RLCA: begin
			`_A <= {`_A[6:0],`_A[7]};
			`_F <= {`_F[7:5],`_A[7],`_F[3:0]};
		end
		`INSN_alu_RRCA: begin
			`_A <= {`_A[0],`_A[7:1]};
			`_F <= {`_F[7:5],`_A[0],`_F[3:0]};
		end
		`INSN_alu_RLA: begin
			`_A <= {`_A[6:0],`_F[4]};
			`_F <= {`_F[7:5],`_A[7],`_F[3:0]};
		end
		`INSN_alu_RRA: begin
			`_A <= {`_F[4],`_A[7:1]};
			`_F <= {`_F[7:5],`_A[0],`_F[3:0]};
		end
		`INSN_alu_DAA: begin
			if (`_F[6]) begin				
				if (`_F[4]) begin
					if(`_A[3:0] >= 4'h6 && `_A[7:4] >= 4'h6 && `F[5]) begin
						`_A <= `_A + 8'h9A;
						`_F <= {((`_A + 8'h9A) == 8'b0), `_F[6:0]};
					end
					else begin
						`_A <= `_A + 8'hA0;
						`_F <= {((`_A + 8'hA0) == 8'b0), `_F[6:0]};
					end
				end
				else begin
					if(`_A[3:0] <= 4'h9 && `_A[7:4] <= 4'h9 && !`_F[5]) begin
						`_F <= {(`_A == 8'b0), `_F[6:0]};
					end
					else begin
						`_A <= `_A + 8'hFA;
						`_F <= {((`_A + 8'hFA) == 8'b0), `_F[6:0]};
					end
				end
			end
			else begin
				if (`_F[4]) begin
					if(`_F[5]) begin
						`_A <= `_A + 8'h66;
						`_F <= {((`_A + 8'h66) == 8'b0), `_F[6:0]};
					end
					else if (`_A[3:0] > 4'b9) begin
						`_A <= `_A + 8'h66;
						`_F <= {((`_A + 8'h66) == 8'b0), `_F[6:0]};
					end
					else begin
						`_A <= `_A + 8'h60;
						`_F <= {((`_A + 8'h60) == 8'b0), `_F[6:0]};
					end
				end
				else begin
					if(`_F[5]) begin
						if(`_A[7:4] > 4'h9) begin
							`_A <= `_A + 8'h66;
							`_F <= {((`_A + 8'h66) == 8'b0), `_F[6:5], 1'b1, `_F[3:0]};
						end
						else begin
							`_A <= `_A + 8'h06;
							`_F <= {((`_A + 8'h06) == 8'b0), `_F[6:0]};
						end
					end
					else begin
						if(`_A[3:0] > 4'h9) begin
							if (`_A[7:4] > 4'h8) begin
								`_A <= `_A + 8'h66;
								`_F <= {((`_A + 8'h66) == 8'b0), `_F[6:5], 1'b1, `_F[3:0]};
							end
							else begin
								`_A <= `_A + 8'h06;
								`_F <= {((`_A + 8'h06) == 8'b0), `_F[6:0]};
							end
						end
						else begin
							if (`_A[7:4] > 4'h9) begin
								`_A <= `_A + 8'h66;
								`_F <= {((`_A + 8'h66) == 8'b0), `_F[6:5], 1'b1, `_F[3:0]};
							end
							else begin
								`_F <= {(`_A == 8'b0), `_F[6:0]};
							end
						end
					end
				end
			end
		end
		`INSN_alu_CPL: begin
			`_A <= ~`_A;
			`_F <= {`_F[7],1'b1,1'b1,`_F[4:0]};
		end
		`INSN_alu_SCF: begin
			`_F <= {`_F[7:5],1'b1,`_F[3:0]};
		end
		`INSN_alu_CCF: begin
			`_F <= {`_F[7:5],~`_F[4],`_F[3:0]};
		end
		endcase
	end
`endif