Merge branch 'master' of lu@anyus.res.cmu.edu:/storage/fpga/FPGABoy

[fpgaboy.git] / core / insn_alu_a.v

`define INSN_alu_RLCA		3'b000
`define INSN_alu_RRCA		3'b001
`define INSN_alu_RLA		3'b010
`define INSN_alu_RRA		3'b011
`define INSN_alu_DAA		3'b100
`define INSN_alu_CPL		3'b101
`define INSN_alu_SCF		3'b110
`define INSN_alu_CCF		3'b111

`define INSN_ALU_A		9'b000xxx111

`ifdef EXECUTE
	`INSN_ALU_A: begin
		`EXEC_NEWCYCLE
		`EXEC_INC_PC
	end
`endif

`ifdef WRITEBACK
	`INSN_ALU_A: begin
		case(opcode[5:3])
		`INSN_alu_RLCA: begin
			`_A <= {`_A[6:0],`_A[7]};
			`_F <= {`_F[7:5],`_A[7],`_F[3:0]};
		end
		`INSN_alu_RRCA: begin
			`_A <= {`_A[0],`_A[7:1]};
			`_F <= {`_F[7:5],`_A[0],`_F[3:0]};
		end
		`INSN_alu_RLA: begin
			`_A <= {`_A[6:0],`_F[4]};
			`_F <= {`_F[7:5],`_A[7],`_F[3:0]};
		end
		`INSN_alu_RRA: begin
			`_A <= {`_A[4],`_A[7:1]};
			`_F <= {`_F[7:5],`_A[0],`_F[3:0]};
		end
		`INSN_alu_CPL: begin
			`_A <= ~`_A;
			`_F <= {`_F[7],1'b1,1'b1,`_F[4:0]};
		end
		`INSN_alu_SCF: begin
			`_F <= {`_F[7:5],1'b1,`_F[3:0]};
		end
		`INSN_alu_CCF: begin
			`_F <= {`_F[7:5],~`_F[4],`_F[3:0]};
		end
		endcase
	end
`endif