impact.cmd fix again
[fpgaboy.git] / LCDC.v
CommitLineData
537e1f83
JW
1`define ADDR_LCDC 16'hFF40
2`define ADDR_STAT 16'hFF41
3`define ADDR_SCY 16'hFF42
4`define ADDR_SCX 16'hFF43
5`define ADDR_LY 16'hFF44
6`define ADDR_LYC 16'hFF45
7`define ADDR_DMA 16'hFF46
8`define ADDR_BGP 16'hFF47
9`define ADDR_OBP0 16'hFF48
10`define ADDR_OBP1 16'hFF49
11`define ADDR_WY 16'hFF4A
12`define ADDR_WX 16'hFF4B
13
14module LCDC(
15 input [15:0] addr,
16 inout [7:0] data,
17 input clk, // 8MHz clock
18 input wr, rd,
00573fd5
JW
19 output wire lcdcirq,
20 output wire vblankirq,
fe3dc890
JW
21 output wire lcdclk, lcdvs, lcdhs,
22 output wire [2:0] lcdr, lcdg, output wire [1:0] lcdb);
537e1f83
JW
23
24 /***** Internal clock that is stable and does not depend on CPU in single/double clock mode *****/
25 reg clk4 = 0;
26 always @(posedge clk)
27 clk4 = ~clk4;
fe3dc890 28 assign lcdclk = clk4;
537e1f83 29
2b7d78b5
JW
30 /***** Video RAM *****/
31 /* Base is 0x8000
32 *
33 * Tile data from 8000-8FFF or 8800-97FF
34 * Background tile maps 9800-9BFF or 9C00-9FFF
35 */
36 reg [7:0] tiledata [6143:0];
37 reg [7:0] bgmap1 [1023:0];
38 reg [7:0] bgmap2 [1023:0];
39
00573fd5
JW
40 /***** LCD control registers *****/
41 reg [7:0] rLCDC = 8'h91;
42 reg [7:0] rSTAT = 8'h00;
43 reg [7:0] rSCY = 8'b00;
44 reg [7:0] rSCX = 8'b00;
45 reg [7:0] rLYC = 8'b00;
46 reg [7:0] rDMA = 8'b00;
47 reg [7:0] rBGP = 8'b00;
48 reg [7:0] rOBP0 = 8'b00;
49 reg [7:0] rOBP1 = 8'b00;
50 reg [7:0] rWY = 8'b00;
51 reg [7:0] rWX = 8'b00;
52
537e1f83
JW
53 /***** Sync generation *****/
54
55 /* A complete cycle takes 456 clocks.
56 * VBlank lasts 4560 clocks (10 scanlines) -- LY = 144 - 153.
57 *
58 * Modes: 0 -> in hblank and OAM/VRAM available - present 207 clks
59 * 1 -> in vblank and OAM/VRAM available
60 * 2 -> OAM in use - present 83 clks
61 * 3 -> OAM/VRAM in use - present 166 clks
62 * So, X = 0~165 is HActive,
63 * X = 166-372 is HBlank,
64 * X = 373-455 is HWhirrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr.
fe3dc890
JW
65 * [02:15:10] <Judge_> LY is updated near the 0 -> 2 transition
66 * [02:15:38] <Judge_> it seems to be updated internally first before it is visible in the LY register itself
67 * [02:15:40] <Judge_> some kind of delay
68 * [02:16:19] <Judge_> iirc it is updated about 4 cycles prior to mode 2
537e1f83
JW
69 */
70 reg [8:0] posx = 9'h000;
71 reg [7:0] posy = 8'h00;
72 wire [1:0] mode = (posy < 144) ?
73 ((posx < 166) ? 2'b11 :
74 (posx < 373) ? 2'b00 :
75 2'b10)
76 : 2'b01;
77
fe3dc890
JW
78 assign lcdvs = (posy == 153) && (posx == 455);
79 assign lcdhs = (posx == 455);
80 assign lcdr = (posx < 160) && (posy < 144) ? {posy == rLYC ? 3'b111 : 3'b000} : 3'b000;
81 assign lcdg = (posx < 160) && (posy < 144) ? {posy < rSCY ? 3'b111 : 3'b000} : 3'b000;
82 assign lcdb = (posx < 160) && (posy < 144) ? {2'b11} : 2'b00;
00573fd5
JW
83
84 reg mode00irq = 0, mode01irq = 0, mode10irq = 0, lycirq = 0;
85 assign lcdcirq = (rSTAT[3] & mode00irq) | (rSTAT[4] & mode01irq) | (rSTAT[5] & mode10irq) | (rSTAT[6] & lycirq);
86 assign vblankirq = (posx == 0 && posy == 153);
87
88 always @(posedge clk4)
537e1f83
JW
89 begin
90 if (posx == 455) begin
91 posx <= 0;
00573fd5 92 if (posy == 153) begin
537e1f83 93 posy <= 0;
00573fd5
JW
94 if (0 == rLYC)
95 lycirq <= 1;
96 end else begin
537e1f83 97 posy <= posy + 1;
00573fd5
JW
98 /* Check for vblank and generate an IRQ if needed. */
99 if (posy == 143) begin
100 mode01irq <= 1;
101 end
102 if ((posy + 1) == rLYC)
103 lycirq <= 1;
104
105 end
106 end else begin
537e1f83 107 posx <= posx + 1;
00573fd5
JW
108 if (posx == 165)
109 mode00irq <= 1;
110 else if (posx == 373)
111 mode10irq <= 1;
112 else begin
113 mode00irq <= 0;
114 mode01irq <= 0;
115 mode10irq <= 0;
116 end
117 lycirq <= 0;
118 end
119
537e1f83
JW
120 end
121
122 /***** Bus interface *****/
537e1f83
JW
123 assign data = rd ?
124 (addr == `ADDR_LCDC) ? rLCDC :
125 (addr == `ADDR_STAT) ? {rSTAT[7:3], (rLYC == posy) ? 1'b1 : 1'b0, mode} :
126 (addr == `ADDR_SCY) ? rSCY :
127 (addr == `ADDR_SCX) ? rSCX :
128 (addr == `ADDR_LY) ? posy :
129 (addr == `ADDR_LYC) ? rLYC :
130 (addr == `ADDR_BGP) ? rBGP :
131 (addr == `ADDR_OBP0) ? rOBP0 :
132 (addr == `ADDR_OBP1) ? rOBP1 :
133 (addr == `ADDR_WY) ? rWY :
134 (addr == `ADDR_WX) ? rWX :
135 8'bzzzzzzzz :
136 8'bzzzzzzzz;
137
138 always @(negedge clk)
139 begin
140 if (wr)
141 case (addr)
142 `ADDR_LCDC: rLCDC <= data;
143 `ADDR_STAT: rSTAT <= {data[7:2],rSTAT[1:0]};
144 `ADDR_SCY: rSCY <= data;
145 `ADDR_SCX: rSCX <= data;
146 `ADDR_LYC: rLYC <= data;
147 `ADDR_DMA: rDMA <= data;
148 `ADDR_BGP: rBGP <= data;
149 `ADDR_OBP0: rOBP0 <= data;
150 `ADDR_OBP1: rOBP1 <= data;
151 `ADDR_WY: rWY <= data;
152 `ADDR_WX: rWX <= data;
153 endcase
154 end
155endmodule
This page took 0.031221 seconds and 4 git commands to generate.