Poke impact.cmd to be movable
[fpgaboy.git] / LCDC.v
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1`define ADDR_LCDC 16'hFF40
2`define ADDR_STAT 16'hFF41
3`define ADDR_SCY 16'hFF42
4`define ADDR_SCX 16'hFF43
5`define ADDR_LY 16'hFF44
6`define ADDR_LYC 16'hFF45
7`define ADDR_DMA 16'hFF46
8`define ADDR_BGP 16'hFF47
9`define ADDR_OBP0 16'hFF48
10`define ADDR_OBP1 16'hFF49
11`define ADDR_WY 16'hFF4A
12`define ADDR_WX 16'hFF4B
13
14module LCDC(
15 input [15:0] addr,
16 inout [7:0] data,
17 input clk, // 8MHz clock
18 input wr, rd,
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19 output wire lcdcirq,
20 output wire vblankirq,
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21 output wire lcdclk, lcdvs, lcdhs,
22 output wire [2:0] lcdr, lcdg, output wire [1:0] lcdb);
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23
24 /***** Internal clock that is stable and does not depend on CPU in single/double clock mode *****/
25 reg clk4 = 0;
26 always @(posedge clk)
27 clk4 = ~clk4;
fe3dc890 28 assign lcdclk = clk4;
537e1f83 29
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30 /***** LCD control registers *****/
31 reg [7:0] rLCDC = 8'h91;
32 reg [7:0] rSTAT = 8'h00;
33 reg [7:0] rSCY = 8'b00;
34 reg [7:0] rSCX = 8'b00;
35 reg [7:0] rLYC = 8'b00;
36 reg [7:0] rDMA = 8'b00;
37 reg [7:0] rBGP = 8'b00;
38 reg [7:0] rOBP0 = 8'b00;
39 reg [7:0] rOBP1 = 8'b00;
40 reg [7:0] rWY = 8'b00;
41 reg [7:0] rWX = 8'b00;
42
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43 /***** Sync generation *****/
44
45 /* A complete cycle takes 456 clocks.
46 * VBlank lasts 4560 clocks (10 scanlines) -- LY = 144 - 153.
47 *
48 * Modes: 0 -> in hblank and OAM/VRAM available - present 207 clks
49 * 1 -> in vblank and OAM/VRAM available
50 * 2 -> OAM in use - present 83 clks
51 * 3 -> OAM/VRAM in use - present 166 clks
52 * So, X = 0~165 is HActive,
53 * X = 166-372 is HBlank,
54 * X = 373-455 is HWhirrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr.
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55 * [02:15:10] <Judge_> LY is updated near the 0 -> 2 transition
56 * [02:15:38] <Judge_> it seems to be updated internally first before it is visible in the LY register itself
57 * [02:15:40] <Judge_> some kind of delay
58 * [02:16:19] <Judge_> iirc it is updated about 4 cycles prior to mode 2
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59 */
60 reg [8:0] posx = 9'h000;
61 reg [7:0] posy = 8'h00;
62 wire [1:0] mode = (posy < 144) ?
63 ((posx < 166) ? 2'b11 :
64 (posx < 373) ? 2'b00 :
65 2'b10)
66 : 2'b01;
67
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68 assign lcdvs = (posy == 153) && (posx == 455);
69 assign lcdhs = (posx == 455);
70 assign lcdr = (posx < 160) && (posy < 144) ? {posy == rLYC ? 3'b111 : 3'b000} : 3'b000;
71 assign lcdg = (posx < 160) && (posy < 144) ? {posy < rSCY ? 3'b111 : 3'b000} : 3'b000;
72 assign lcdb = (posx < 160) && (posy < 144) ? {2'b11} : 2'b00;
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73
74 reg mode00irq = 0, mode01irq = 0, mode10irq = 0, lycirq = 0;
75 assign lcdcirq = (rSTAT[3] & mode00irq) | (rSTAT[4] & mode01irq) | (rSTAT[5] & mode10irq) | (rSTAT[6] & lycirq);
76 assign vblankirq = (posx == 0 && posy == 153);
77
78 always @(posedge clk4)
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79 begin
80 if (posx == 455) begin
81 posx <= 0;
00573fd5 82 if (posy == 153) begin
537e1f83 83 posy <= 0;
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84 if (0 == rLYC)
85 lycirq <= 1;
86 end else begin
537e1f83 87 posy <= posy + 1;
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88 /* Check for vblank and generate an IRQ if needed. */
89 if (posy == 143) begin
90 mode01irq <= 1;
91 end
92 if ((posy + 1) == rLYC)
93 lycirq <= 1;
94
95 end
96 end else begin
537e1f83 97 posx <= posx + 1;
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98 if (posx == 165)
99 mode00irq <= 1;
100 else if (posx == 373)
101 mode10irq <= 1;
102 else begin
103 mode00irq <= 0;
104 mode01irq <= 0;
105 mode10irq <= 0;
106 end
107 lycirq <= 0;
108 end
109
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110 end
111
112 /***** Bus interface *****/
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113 assign data = rd ?
114 (addr == `ADDR_LCDC) ? rLCDC :
115 (addr == `ADDR_STAT) ? {rSTAT[7:3], (rLYC == posy) ? 1'b1 : 1'b0, mode} :
116 (addr == `ADDR_SCY) ? rSCY :
117 (addr == `ADDR_SCX) ? rSCX :
118 (addr == `ADDR_LY) ? posy :
119 (addr == `ADDR_LYC) ? rLYC :
120 (addr == `ADDR_BGP) ? rBGP :
121 (addr == `ADDR_OBP0) ? rOBP0 :
122 (addr == `ADDR_OBP1) ? rOBP1 :
123 (addr == `ADDR_WY) ? rWY :
124 (addr == `ADDR_WX) ? rWX :
125 8'bzzzzzzzz :
126 8'bzzzzzzzz;
127
128 always @(negedge clk)
129 begin
130 if (wr)
131 case (addr)
132 `ADDR_LCDC: rLCDC <= data;
133 `ADDR_STAT: rSTAT <= {data[7:2],rSTAT[1:0]};
134 `ADDR_SCY: rSCY <= data;
135 `ADDR_SCX: rSCX <= data;
136 `ADDR_LYC: rLYC <= data;
137 `ADDR_DMA: rDMA <= data;
138 `ADDR_BGP: rBGP <= data;
139 `ADDR_OBP0: rOBP0 <= data;
140 `ADDR_OBP1: rOBP1 <= data;
141 `ADDR_WY: rWY <= data;
142 `ADDR_WX: rWX <= data;
143 endcase
144 end
145endmodule
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