[fpgaboy.git] / insn_ld_hl_reg.v

`ifdef EXECUTE
	`INSN_LD_HL_reg: begin
		case (cycle)
		0:	begin
				case (opcode[2:0])
				`INSN_reg_A:	wdata <= registers[`REG_A];
				`INSN_reg_B:	wdata <= registers[`REG_B];
				`INSN_reg_C:	wdata <= registers[`REG_C];
				`INSN_reg_D:	wdata <= registers[`REG_D];
				`INSN_reg_E:	wdata <= registers[`REG_E];
				`INSN_reg_H:	wdata <= registers[`REG_H];
				`INSN_reg_L:	wdata <= registers[`REG_L];
				endcase
				address <= {registers[`REG_H], registers[`REG_L]};
				wr <= 1; rd <= 0;
			end
		1:	begin
				`EXEC_INC_PC;
				`EXEC_NEWCYCLE;
			end
		endcase
	end
`endif

`ifdef WRITEBACK
	`INSN_LD_HL_reg: begin
		/* Nothing of interest here */
	end
`endif
Commit	Line	Data
81358c71 JW	1	`ifdef EXECUTE
	2	`INSN_LD_HL_reg: begin
	3	case (cycle)
	4	0: begin
	5	case (opcode[2:0])
	6	`INSN_reg_A: wdata <= registers[`REG_A];
	7	`INSN_reg_B: wdata <= registers[`REG_B];
	8	`INSN_reg_C: wdata <= registers[`REG_C];
	9	`INSN_reg_D: wdata <= registers[`REG_D];
	10	`INSN_reg_E: wdata <= registers[`REG_E];
	11	`INSN_reg_H: wdata <= registers[`REG_H];
	12	`INSN_reg_L: wdata <= registers[`REG_L];
	13	endcase
	14	address <= {registers[`REG_H], registers[`REG_L]};
	15	wr <= 1; rd <= 0;
	16	end
	17	1: begin
	18	`EXEC_INC_PC;
	19	`EXEC_NEWCYCLE;
	20	end
	21	endcase
	22	end
	23	`endif
	24
	25	`ifdef WRITEBACK
	26	`INSN_LD_HL_reg: begin
	27	/* Nothing of interest here */
	28	end
	29	`endif