[fpgaboy.git] / insn_jp-jpcc.v

`ifdef EXECUTE
	`INSN_JP_imm,`INSN_JPCC_imm: begin
		case (cycle)
		0:	begin
				`EXEC_INC_PC;
				`EXEC_NEXTADDR_PCINC;
				rd <= 1;
			end
		1:	begin
				`EXEC_INC_PC;
				`EXEC_NEXTADDR_PCINC;
				rd <= 1;
			end
		2:	begin
				`EXEC_INC_PC;
				if (!opcode[0]) begin	// i.e., JP cc,nn
					/* We need to check the condition code to bail out. */
					case (opcode[4:3])
					`INSN_cc_NZ:	if (registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end
					`INSN_cc_Z:	if (~registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end
					`INSN_cc_NC:	if (registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end
					`INSN_cc_C:	if (~registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end
					endcase
				end
			end
		3:	begin
				`EXEC_NEWCYCLE;
			end
		endcase
	end
`endif

`ifdef WRITEBACK
	`INSN_JP_imm,`INSN_JPCC_imm: begin
		case (cycle)
		0:	begin /* type F */ end
		1:	tmp <= rdata;	// tmp contains newpcl
		2:	tmp2 <= rdata;	// tmp2 contains newpch
		3:	{registers[`REG_PCH],registers[`REG_PCL]} <=
				{tmp2,tmp};
		endcase
	end
`endif
Commit	Line	Data
df770340 JW	1	`ifdef EXECUTE
	2	`INSN_JP_imm,`INSN_JPCC_imm: begin
	3	case (cycle)
	4	0: begin
	5	`EXEC_INC_PC;
	6	`EXEC_NEXTADDR_PCINC;
	7	rd <= 1;
	8	end
	9	1: begin
	10	`EXEC_INC_PC;
	11	`EXEC_NEXTADDR_PCINC;
	12	rd <= 1;
	13	end
	14	2: begin
	15	`EXEC_INC_PC;
	16	if (!opcode[0]) begin // i.e., JP cc,nn
	17	/* We need to check the condition code to bail out. */
	18	case (opcode[4:3])
	19	`INSN_cc_NZ: if (registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end
	20	`INSN_cc_Z: if (~registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end
	21	`INSN_cc_NC: if (registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end
	22	`INSN_cc_C: if (~registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end
	23	endcase
	24	end
	25	end
	26	3: begin
	27	`EXEC_NEWCYCLE;
	28	end
	29	endcase
	30	end
	31	`endif
	32
	33	`ifdef WRITEBACK
	34	`INSN_JP_imm,`INSN_JPCC_imm: begin
	35	case (cycle)
	36	0: begin /* type F */ end
	37	1: tmp <= rdata; // tmp contains newpcl
	38	2: tmp2 <= rdata; // tmp2 contains newpch
	39	3: {registers[`REG_PCH],registers[`REG_PCL]} <=
	40	{tmp2,tmp};
	41	endcase
	42	end
	43	`endif