Fix tileaddr bug. Make bus interface more explicit.
[fpgaboy.git] / LCDC.v
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1`define ADDR_LCDC 16'hFF40
2`define ADDR_STAT 16'hFF41
3`define ADDR_SCY 16'hFF42
4`define ADDR_SCX 16'hFF43
5`define ADDR_LY 16'hFF44
6`define ADDR_LYC 16'hFF45
7`define ADDR_DMA 16'hFF46
8`define ADDR_BGP 16'hFF47
9`define ADDR_OBP0 16'hFF48
10`define ADDR_OBP1 16'hFF49
11`define ADDR_WY 16'hFF4A
12`define ADDR_WX 16'hFF4B
13
14module LCDC(
15 input [15:0] addr,
16 inout [7:0] data,
17 input clk, // 8MHz clock
18 input wr, rd,
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19 output wire lcdcirq,
20 output wire vblankirq,
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21 output wire lcdclk, lcdvs, lcdhs,
22 output wire [2:0] lcdr, lcdg, output wire [1:0] lcdb);
537e1f83 23
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24 /***** Needed prototypes *****/
25 wire [1:0] pixdata;
26
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27 /***** Internal clock that is stable and does not depend on CPU in single/double clock mode *****/
28 reg clk4 = 0;
29 always @(posedge clk)
30 clk4 = ~clk4;
fe3dc890 31 assign lcdclk = clk4;
537e1f83 32
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33 /***** LCD control registers *****/
34 reg [7:0] rLCDC = 8'h91;
35 reg [7:0] rSTAT = 8'h00;
36 reg [7:0] rSCY = 8'b00;
37 reg [7:0] rSCX = 8'b00;
38 reg [7:0] rLYC = 8'b00;
39 reg [7:0] rDMA = 8'b00;
40 reg [7:0] rBGP = 8'b00;
41 reg [7:0] rOBP0 = 8'b00;
42 reg [7:0] rOBP1 = 8'b00;
43 reg [7:0] rWY = 8'b00;
44 reg [7:0] rWX = 8'b00;
45
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46 /***** Sync generation *****/
47
48 /* A complete cycle takes 456 clocks.
49 * VBlank lasts 4560 clocks (10 scanlines) -- LY = 144 - 153.
50 *
51 * Modes: 0 -> in hblank and OAM/VRAM available - present 207 clks
52 * 1 -> in vblank and OAM/VRAM available
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53 * 2 -> OAM in use - present 86 clks
54 * 3 -> OAM/VRAM in use - present 163 clks
55 * So, X = 0~162 is HActive,
56 * X = 163-369 is HBlank,
57 * X = 370-455 is HWhirrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr.
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58 * [02:15:10] <Judge_> LY is updated near the 0 -> 2 transition
59 * [02:15:38] <Judge_> it seems to be updated internally first before it is visible in the LY register itself
60 * [02:15:40] <Judge_> some kind of delay
61 * [02:16:19] <Judge_> iirc it is updated about 4 cycles prior to mode 2
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62 */
63 reg [8:0] posx = 9'h000;
64 reg [7:0] posy = 8'h00;
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65
66 wire vraminuse = (posx < 163);
67 wire oaminuse = (posx > 369);
68
69 wire display = (posx > 2) && (posx < 163) && (posy < 144);
70
537e1f83 71 wire [1:0] mode = (posy < 144) ?
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72 (vraminuse ? 2'b11 :
73 oaminuse ? 2'b10 :
74 2'b00)
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75 : 2'b01;
76
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77 wire [7:0] vxpos = rSCX + posx - 3;
78 wire [7:0] vypos = rSCY + posy;
79
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80 assign lcdvs = (posy == 153) && (posx == 455);
81 assign lcdhs = (posx == 455);
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82 assign lcdr = display ? {pixdata[1] ? 3'b111 : 3'b000} : 3'b000;
83 assign lcdg = display ? {pixdata[0] ? 3'b111 : 3'b000} : 3'b000;
4d90f272 84 assign lcdb = display ? {(vypos < 8) ? 2'b11 : 2'b00} : 2'b00;
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85
86 reg mode00irq = 0, mode01irq = 0, mode10irq = 0, lycirq = 0;
87 assign lcdcirq = (rSTAT[3] & mode00irq) | (rSTAT[4] & mode01irq) | (rSTAT[5] & mode10irq) | (rSTAT[6] & lycirq);
88 assign vblankirq = (posx == 0 && posy == 153);
89
90 always @(posedge clk4)
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91 begin
92 if (posx == 455) begin
93 posx <= 0;
00573fd5 94 if (posy == 153) begin
537e1f83 95 posy <= 0;
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96 if (0 == rLYC)
97 lycirq <= 1;
98 end else begin
537e1f83 99 posy <= posy + 1;
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100 /* Check for vblank and generate an IRQ if needed. */
101 if (posy == 143) begin
102 mode01irq <= 1;
103 end
104 if ((posy + 1) == rLYC)
105 lycirq <= 1;
106
107 end
108 end else begin
537e1f83 109 posx <= posx + 1;
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110 if (posx == 165)
111 mode00irq <= 1;
112 else if (posx == 373)
113 mode10irq <= 1;
114 else begin
115 mode00irq <= 0;
116 mode01irq <= 0;
117 mode10irq <= 0;
118 end
119 lycirq <= 0;
120 end
537e1f83 121 end
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122
123 /***** Video RAM *****/
124 /* Base is 0x8000
125 *
126 * Tile data from 8000-8FFF or 8800-97FF
127 * Background tile maps 9800-9BFF or 9C00-9FFF
128 */
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129 reg [7:0] tiledatahigh [3071:0];
130 reg [7:0] tiledatalow [3071:0];
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131 reg [7:0] bgmap1 [1023:0];
132 reg [7:0] bgmap2 [1023:0];
133
134 // Upper five bits are Y coord, lower five bits are X coord
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135 // The new tile number is loaded when vxpos[2:0] is 3'b110
136 // The new tile data is loaded when vxpos[2:0] is 3'b111
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137 // The new tile data is latched and ready when vxpos[2:0] is 3'b000!
138 wire [9:0] bgmapaddr = {vypos[7:3], vxpos[7:3]};
139 reg [7:0] tileno;
75be7c71 140 wire [10:0] tileaddr = {tileno, vypos[2:0]};
4d90f272 141 reg [7:0] tilehigh, tilelow;
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142 assign pixdata = {tilehigh[vxpos[2:0]], tilelow[vxpos[2:0]]};
143
144 wire decode_tiledata = (addr >= 16'h8000) && (addr <= 16'h97FF);
145 wire decode_bgmap1 = (addr >= 16'h9800) && (addr <= 16'h9BFF);
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146
147 wire [9:0] bgmapaddr_in = vraminuse ? bgmapaddr : addr[9:0];
148 wire [11:0] tileaddr_in = vraminuse ? tileaddr : addr[12:1];
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149
150 always @(negedge clk)
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151 if ((vraminuse && ((posx == 1) || ((posx > 2) && (vxpos[2:0] == 3'b110)))) || decode_bgmap1) begin
152 tileno <= bgmap1[bgmapaddr_in];
153 if (wr && decode_bgmap1)
154 bgmap1[bgmapaddr_in] <= data;
155 end
156
157 always @(negedge clk)
158 if ((vraminuse && ((posx == 2) || ((posx > 2) && (vxpos[2:0] == 3'b111)))) || decode_tiledata) begin
159 tilehigh <= tiledatahigh[tileaddr_in];
160 tilelow <= tiledatalow[tileaddr_in];
161 if (wr && addr[0] && decode_tiledata)
162 tiledatahigh[tileaddr_in] <= data;
163 if (wr && ~addr[0] && decode_tiledata)
164 tiledatalow[tileaddr_in] <= data;
39a68cde 165 end
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166
167 /***** Bus interface *****/
537e1f83 168 assign data = rd ?
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169 ((addr == `ADDR_LCDC) ? rLCDC :
170 (addr == `ADDR_STAT) ? {rSTAT[7:3], (rLYC == posy) ? 1'b1 : 1'b0, mode} :
171 (addr == `ADDR_SCY) ? rSCY :
172 (addr == `ADDR_SCX) ? rSCX :
173 (addr == `ADDR_LY) ? posy :
174 (addr == `ADDR_LYC) ? rLYC :
175 (addr == `ADDR_BGP) ? rBGP :
176 (addr == `ADDR_OBP0) ? rOBP0 :
177 (addr == `ADDR_OBP1) ? rOBP1 :
178 (addr == `ADDR_WY) ? rWY :
179 (addr == `ADDR_WX) ? rWX :
180 (decode_tiledata && addr[0]) ? tilehigh :
181 (decode_tiledata && ~addr[0]) ? tilelow :
182 (decode_bgmap1) ? tileno :
183 8'bzzzzzzzz) :
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184 8'bzzzzzzzz;
185
186 always @(negedge clk)
187 begin
188 if (wr)
189 case (addr)
190 `ADDR_LCDC: rLCDC <= data;
191 `ADDR_STAT: rSTAT <= {data[7:2],rSTAT[1:0]};
192 `ADDR_SCY: rSCY <= data;
193 `ADDR_SCX: rSCX <= data;
194 `ADDR_LYC: rLYC <= data;
195 `ADDR_DMA: rDMA <= data;
196 `ADDR_BGP: rBGP <= data;
197 `ADDR_OBP0: rOBP0 <= data;
198 `ADDR_OBP1: rOBP1 <= data;
199 `ADDR_WY: rWY <= data;
200 `ADDR_WX: rWX <= data;
201 endcase
202 end
203endmodule
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