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[fpgaboy.git] / Uart.v
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7d9d69c7 1`define IN_CLK 8388608
f888201b 2`define OUT_CLK 57600
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3`define CLK_DIV `IN_CLK / `OUT_CLK
4`define MMAP_ADDR 16'hFF50
5
6module UART(
7 input clk,
8 input wr,
9 input rd,
10 input [15:0] addr,
a85b19a7 11 inout [7:0] data,
1e26cecc 12 output reg serial = 1);
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13
14 wire decode = (addr == `MMAP_ADDR);
15
16 wire [7:0] odata;
17 assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
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18
19 reg [7:0] data_stor = 0;
20 reg [15:0] clkdiv = 0;
21 reg have_data = 0;
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22 reg [3:0] diqing = 4'b0000;
23
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24 wire new = (wr) && (!have_data) && decode;
25
26 assign odata = have_data ? 8'b1 : 8'b0;
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27
28 always @ (negedge clk)
29 begin
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30 /* deal with diqing */
31 if(new) begin
7d9d69c7 32 data_stor <= data;
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33 have_data <= 1;
34 diqing <= 4'b0000;
35 end else if (clkdiv == 0) begin
36 diqing <= diqing + 1;
37 if (have_data)
38 case (diqing)
7d9d69c7 39 4'b0000: serial <= 0;
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40 4'b0001: serial <= data_stor[0];
41 4'b0010: serial <= data_stor[1];
42 4'b0011: serial <= data_stor[2];
43 4'b0100: serial <= data_stor[3];
44 4'b0101: serial <= data_stor[4];
45 4'b0110: serial <= data_stor[5];
46 4'b0111: serial <= data_stor[6];
47 4'b1000: serial <= data_stor[7];
7d9d69c7 48 4'b1001: serial <= 1;
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49 4'b1010: have_data <= 0;
50 default: $stop;
51 endcase
52 end
53
54 /* deal with clkdiv */
55 if((new && !have_data) || clkdiv == `CLK_DIV)
56 clkdiv <= 0;
57 else
58 clkdiv <= clkdiv + 1;
59 end
60endmodule
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