git.joshuawise.com / fpgaboy.git / blame
| Commit | Line | Data |
|---|---|---|
| a0267255 JW |
1 | `define IN_CLK 8400000 |
| 2 | `define OUT_CLK 9600 | |
| 3 | `define CLK_DIV `IN_CLK / `OUT_CLK | |
| 4 | `define MMAP_ADDR 16'hFF50 | |
| 5 | ||
| 6 | module UART( | |
| 7 | input clk, | |
| 8 | input wr, | |
| 9 | input rd, | |
| 10 | input [15:0] addr, | |
| 11 | input [7:0] data, | |
| 12 | output reg serial); | |
| 13 | ||
| 14 | reg [7:0] data_stor = 0; | |
| 15 | reg [15:0] clkdiv = 0; | |
| 16 | reg have_data = 0; | |
| 17 | reg data_end = 0; | |
| 18 | reg [3:0] diqing = 4'b0000; | |
| 19 | ||
| 20 | wire new = (wr) && (!have_data) && (addr == `MMAP_ADDR); | |
| 21 | ||
| 22 | always @ (negedge clk) | |
| 23 | begin | |
| 24 | `define FUQING 4'b1010 | |
| 25 | /* deal with diqing */ | |
| 26 | if(new) begin | |
| 27 | data_stor <= ~data; | |
| 28 | have_data <= 1; | |
| 29 | diqing <= 4'b0000; | |
| 30 | end else if (clkdiv == 0) begin | |
| 31 | diqing <= diqing + 1; | |
| 32 | if (have_data) | |
| 33 | case (diqing) | |
| 34 | 4'b0000: serial <= 1; | |
| 35 | 4'b0001: serial <= data_stor[0]; | |
| 36 | 4'b0010: serial <= data_stor[1]; | |
| 37 | 4'b0011: serial <= data_stor[2]; | |
| 38 | 4'b0100: serial <= data_stor[3]; | |
| 39 | 4'b0101: serial <= data_stor[4]; | |
| 40 | 4'b0110: serial <= data_stor[5]; | |
| 41 | 4'b0111: serial <= data_stor[6]; | |
| 42 | 4'b1000: serial <= data_stor[7]; | |
| 43 | 4'b1001: serial <= 0; | |
| 44 | 4'b1010: have_data <= 0; | |
| 45 | default: $stop; | |
| 46 | endcase | |
| 47 | end | |
| 48 | ||
| 49 | /* deal with clkdiv */ | |
| 50 | if((new && !have_data) || clkdiv == `CLK_DIV) | |
| 51 | clkdiv <= 0; | |
| 52 | else | |
| 53 | clkdiv <= clkdiv + 1; | |
| 54 | end | |
| 55 | endmodule |