Fix ld (nn), sp, for real this time.

[fpgaboy.git] / core / insn_ld_hl_reg.v

`define INSN_LD_HL_reg		9'b001110xxx

`ifdef EXECUTE
	`INSN_LD_HL_reg: begin
		case (cycle)
		0:	begin
				case (opcode[2:0])
				`INSN_reg_A:	wdata <= `_A;
				`INSN_reg_B:	wdata <= `_B;
				`INSN_reg_C:	wdata <= `_C;
				`INSN_reg_D:	wdata <= `_D;
				`INSN_reg_E:	wdata <= `_E;
				`INSN_reg_H:	wdata <= `_H;
				`INSN_reg_L:	wdata <= `_L;
				endcase
				address <= `_HL;
				wr <= 1; rd <= 0;
			end
		1:	begin
				`EXEC_INC_PC
				`EXEC_NEWCYCLE
			end
		endcase
	end
`endif

`ifdef WRITEBACK
	`INSN_LD_HL_reg: begin
		/* Nothing of interest here */
	end
`endif