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firearm.git
2008-12-26 Joshua WiseAdd condition checking logic. commit | commitdiff | tree | snapshot
2008-12-26 Joshua WiseCommit flag setter for issue. commit | commitdiff | tree | snapshot
2008-12-26 Joshua WiseUpdate copypasta fodder. commit | commitdiff | tree | snapshot
2008-12-26 Joshua WiseAdd more constants. commit | commitdiff | tree | snapshot
2008-12-26 Joshua WiseAdd some ARM constants. commit | commitdiff | tree | snapshot
2008-12-25 Joshua Wisea bit of issue commit | commitdiff | tree | snapshot
2008-12-24 Joshua WiseAdd the register file. commit | commitdiff | tree | snapshot
2008-12-22 Joshua WiseFix a few scattered bugs, and get fetch to work. commit | commitdiff | tree | snapshot
2008-12-22 Joshua WiseWire the fetch unit into the top module commit | commitdiff | tree | snapshot
2008-12-22 Joshua WiseAdd fetch module commit | commitdiff | tree | snapshot
2008-12-22 Joshua WiseAdd the blockram to the system.v. commit | commitdiff | tree | snapshot
2008-12-22 Joshua WiseAdd the blockram. commit | commitdiff | tree | snapshot
2008-12-22 Joshua Wisesystem.v commit | commitdiff | tree | snapshot
2008-12-20 Joshua WiseBug fixes, and a first cut at a bus arbiter commit | commitdiff | tree | snapshot
2008-12-19 Joshua WiseFix syntax errors and make it compile in verilator. commit | commitdiff | tree | snapshot
2008-12-19 Joshua Wiseactually fill the cache? commit | commitdiff | tree | snapshot
2008-12-19 Joshua Wisesome work on cache filling, and fleshing out a bus... commit | commitdiff | tree | snapshot
2008-09-01 Joshua WiseFix tag position commit | commitdiff | tree | snapshot
2008-09-01 Joshua WiseAdd icache kind of commit | commitdiff | tree | snapshot
FireARM pipelined ARM-like CPU implementation in Verilog
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