Joshua Wise's Git repositories - firearm.git/search

]> Joshua Wise's Git repositories - firearm.git/search

git.joshuawise.com / firearm.git / search

2008-12-26	Joshua Wise	Only emit a stall if we didn't take a bubble in.	commit \| commitdiff \| tree
2008-12-26	Joshua Wise	initialize inflights	commit \| commitdiff \| tree
2008-12-26	Joshua Wise	Wire things up, and fix circular logic in issue.	commit \| commitdiff \| tree
2008-12-26	Joshua Wise	Actually do the issue???	commit \| commitdiff \| tree
2008-12-26	Joshua Wise	Add condition checking logic.	commit \| commitdiff \| tree
2008-12-26	Joshua Wise	Commit flag setter for issue.	commit \| commitdiff \| tree
2008-12-26	Joshua Wise	Update copypasta fodder.	commit \| commitdiff \| tree
2008-12-26	Joshua Wise	Add more constants.	commit \| commitdiff \| tree
2008-12-26	Joshua Wise	Add some ARM constants.	commit \| commitdiff \| tree
2008-12-25	Joshua Wise	a bit of issue	commit \| commitdiff \| tree
2008-12-24	Joshua Wise	Add the register file.	commit \| commitdiff \| tree
2008-12-22	Joshua Wise	Fix a few scattered bugs, and get fetch to work.	commit \| commitdiff \| tree
2008-12-22	Joshua Wise	Wire the fetch unit into the top module	commit \| commitdiff \| tree
2008-12-22	Joshua Wise	Add fetch module	commit \| commitdiff \| tree
2008-12-22	Joshua Wise	Add the blockram to the system.v.	commit \| commitdiff \| tree
2008-12-22	Joshua Wise	Add the blockram.	commit \| commitdiff \| tree
2008-12-22	Joshua Wise	system.v	commit \| commitdiff \| tree
2008-12-20	Joshua Wise	Bug fixes, and a first cut at a bus arbiter	commit \| commitdiff \| tree
2008-12-19	Joshua Wise	Fix syntax errors and make it compile in verilator.	commit \| commitdiff \| tree
2008-12-19	Joshua Wise	actually fill the cache?	commit \| commitdiff \| tree
2008-12-19	Joshua Wise	some work on cache filling, and fleshing out a bus...	commit \| commitdiff \| tree
2008-09-01	Joshua Wise	Fix tag position	commit \| commitdiff \| tree
2008-09-01	Joshua Wise	Add icache kind of	commit \| commitdiff \| tree

FireARM pipelined ARM-like CPU implementation in Verilog

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