Joshua Wise's Git repositories - firearm.git/search

]> Joshua Wise's Git repositories - firearm.git/search

git.joshuawise.com / firearm.git / search

2009-03-18	Joshua Wise	xst: Add synthesis files (part 1).	commit \| commitdiff \| tree
2009-03-18	Joshua Wise	testbench: Add a putc(getc()) loop.	commit \| commitdiff \| tree
2009-03-18	Joshua Wise	Terminal: Fix to have non-blocking assigns in flop...	commit \| commitdiff \| tree
2009-03-17	Joshua Wise	Memory: Add work-around for Xilinx bug in MULT.	commit \| commitdiff \| tree
2009-03-17	Joshua Wise	DCache: Clear out a rw_wait reference in a $display...	commit \| commitdiff \| tree
2009-03-17	Joshua Wise	Fetch: Rewrite for the 317235784th time, this time...	commit \| commitdiff \| tree
2009-02-26	Joshua Wise	Memory: Fix bug in which swp_oldval does not get latched...	commit \| commitdiff \| tree
2009-02-22	Joshua Wise	Memory: Do not progress LSM state machine if rw_wait.	commit \| commitdiff \| tree
2009-02-22	Joshua Wise	Memory: Fix multisource for offset.	commit \| commitdiff \| tree
2008-12-31	Joshua Wise	Execute.v: Execute multiplication happily	commit \| commitdiff \| tree
2008-12-31	Joshua Wise	Issue.v: lol@me; stall was not getting propagated	commit \| commitdiff \| tree
2008-12-31	Joshua Wise	ram{.comments,}.hex: Add a multiplier test.	commit \| commitdiff \| tree
2008-12-31	Joshua Wise	Execute.v: Wire up the ALU.	commit \| commitdiff \| tree
2008-12-31	Joshua Wise	system.v: Add debug output for the execute stage.	commit \| commitdiff \| tree
2008-12-31	Joshua Wise	ram{.comments,}.hex: Add a simple orr instruction....	commit \| commitdiff \| tree
2008-12-22	Joshua Wise	Fix a few scattered bugs, and get fetch to work.	commit \| commitdiff \| tree
2008-12-22	Joshua Wise	Wire the fetch unit into the top module	commit \| commitdiff \| tree
2008-12-22	Joshua Wise	Add fetch module	commit \| commitdiff \| tree
2008-12-22	Joshua Wise	Add the blockram to the system.v.	commit \| commitdiff \| tree
2008-12-22	Joshua Wise	Add the blockram.	commit \| commitdiff \| tree

FireARM pipelined ARM-like CPU implementation in Verilog

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