git.joshuawise.com / firearm.git / search
? search:
summary | shortlog | log | commit | commitdiff | tree
first ⋅ prev ⋅ next
xst: Add synthesis files (part 1).
2009-03-18 Joshua Wisexst: Add synthesis files (part 1).
 commit | commitdiff | tree
2009-03-18 Joshua Wisetestbench: Add a putc(getc()) loop.
 commit | commitdiff | tree
2009-03-18 Joshua WiseTerminal: Fix to have non-blocking assigns in flop...
commit | commitdiff | tree
2009-03-17 Joshua WiseMemory: Add work-around for Xilinx bug in MULT.
 commit | commitdiff | tree
2009-03-17 Joshua WiseDCache: Clear out a rw_wait reference in a $display...
commit | commitdiff | tree
2009-03-17 Joshua WiseFetch: Rewrite for the 317235784th time, this time...
commit | commitdiff | tree
2009-02-26 Joshua WiseMemory: Fix bug in which swp_oldval does not get latched...
commit | commitdiff | tree
2009-02-22 Joshua WiseMemory: Do not progress LSM state machine if rw_wait.
 commit | commitdiff | tree
2009-02-22 Joshua WiseMemory: Fix multisource for offset.
 commit | commitdiff | tree
2008-12-31 Joshua WiseExecute.v: Execute multiplication happily
 commit | commitdiff | tree
2008-12-31 Joshua WiseIssue.v: lol@me; stall was not getting propagated
 commit | commitdiff | tree
2008-12-31 Joshua Wiseram{.comments,}.hex: Add a multiplier test.
 commit | commitdiff | tree
2008-12-31 Joshua WiseExecute.v: Wire up the ALU.
 commit | commitdiff | tree
2008-12-31 Joshua Wisesystem.v: Add debug output for the execute stage.
 commit | commitdiff | tree
2008-12-31 Joshua Wiseram{.comments,}.hex: Add a simple orr instruction....
commit | commitdiff | tree
2008-12-22 Joshua WiseFix a few scattered bugs, and get fetch to work.
 commit | commitdiff | tree
2008-12-22 Joshua WiseWire the fetch unit into the top module
 commit | commitdiff | tree
2008-12-22 Joshua WiseAdd fetch module
 commit | commitdiff | tree
2008-12-22 Joshua WiseAdd the blockram to the system.v.
 commit | commitdiff | tree
2008-12-22 Joshua WiseAdd the blockram.
 commit | commitdiff | tree
FireARM pipelined ARM-like CPU implementation in Verilog
This page took 0.028334 seconds and 3 git commands to generate.