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Memory: Fix multisource for offset.
2009-02-22 Joshua WiseMemory: Fix multisource for offset.
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2008-12-31 Joshua WiseExecute.v: Execute multiplication happily
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2008-12-31 Joshua WiseIssue.v: lol@me; stall was not getting propagated
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2008-12-31 Joshua Wiseram{.comments,}.hex: Add a multiplier test.
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2008-12-31 Joshua WiseExecute.v: Wire up the ALU.
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2008-12-31 Joshua Wisesystem.v: Add debug output for the execute stage.
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2008-12-31 Joshua Wiseram{.comments,}.hex: Add a simple orr instruction....
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2008-12-22 Joshua WiseFix a few scattered bugs, and get fetch to work.
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2008-12-22 Joshua WiseWire the fetch unit into the top module
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2008-12-22 Joshua WiseAdd fetch module
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2008-12-22 Joshua WiseAdd the blockram to the system.v.
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2008-12-22 Joshua WiseAdd the blockram.
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FireARM pipelined ARM-like CPU implementation in Verilog
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