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Execute.v: Add outpc and outinsn. System.v: Add and make wires consistent.
[firearm.git] / Fetch.v
2008-12-28 Joshua WiseMerge nyus:/storage/git/firearm blob | commitdiff | raw
2008-12-28 Joshua WiseFix stupid pc request in Fetch blob | commitdiff | raw
2008-12-26 Joshua WiseMerge nyus:/storage/git/firearm blob | commitdiff | raw | diff to current
2008-12-26 Joshua WiseInitialize more things, and follow more clocking rules. blob | commitdiff | raw | diff to current
2008-12-22 Joshua WiseFix a few scattered bugs, and get fetch to work. blob | commitdiff | raw | diff to current
FireARM pipelined ARM-like CPU implementation in Verilog
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