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Memory: Fix the case where a LDM/LDR/LDRH/STM/STR/STRH would not get rejected if...
authorJoshua Wise <joshua@rebirth.joshuawise.com>
Mon, 19 Jan 2009 09:28:32 +0000 (04:28 -0500)
committerJoshua Wise <joshua@rebirth.joshuawise.com>
Mon, 19 Jan 2009 09:28:32 +0000 (04:28 -0500)
commitd64d6ef9fffab25e5fffa4263e9ceb6ff85267da
tree84630c23d84e9ff48211770dd3df624342f71048tree | snapshot
parent4d7253f1058e6bd63bfc720a5b881e85d99270eecommit | diff
Memory: Fix the case where a LDM/LDR/LDRH/STM/STR/STRH would not get rejected if stall was asserted because of a wait.
Memory.v diff | blob | blame | history
FireARM pipelined ARM-like CPU implementation in Verilog
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