System, Terminal: Provide real-world outputs on non-Verilator to avoid optimizing...

diff --git a/Terminal.v b/Terminal.v
index dd041d0a5dbeb0576398856379922cf652155075..9ddd5d30340bd52dc73cf85b124779573f2753fa 100644 (file)
--- a/Terminal.v
+++ b/Terminal.v
@@ -7,7 +7,14 @@ module Terminal(
        output reg cp_busy,
        input cp_rnw,
        output reg [31:0] cp_read = 0,
        output reg cp_busy,
        input cp_rnw,
        output reg [31:0] cp_read = 0,

-       input [31:0] cp_write);
+       input [31:0] cp_write
+`ifdef verilator
+`else
+       , output reg [8:0] sys_odata = 0,
+       input [8:0] sys_idata,
+       output reg sys_tookdata = 0
+`endif
+);

        
        /* Terminal pretends to be cp5. */
        reg towrite = 0;
        
        /* Terminal pretends to be cp5. */
        reg towrite = 0;


@@ -41,5 +48,16 @@ module Terminal(
                        $c("{extern void term_output(unsigned char d); term_output(",data,");}");
                else if (didread || !indata[8])
                        indata = $c("({extern unsigned int term_input(); term_input();})");
                        $c("{extern void term_output(unsigned char d); term_output(",data,");}");
                else if (didread || !indata[8])
                        indata = $c("({extern unsigned int term_input(); term_input();})");

+`else
+       always @(posedge clk)
+       begin
+               sys_odata = {towrite,data};
+               if (didread || !indata[8])
+               begin
+                       indata = sys_idata;
+                       sys_tookdata = 1;
+               end else
+                       sys_tookdata = 0;
+       end

 `endif
 endmodule
 `endif
 endmodule

diff --git a/system.v b/system.v
index 07adfd88ac963c3c908c9602b2161f3dfe96533e..f134ffcab95c343545728ea7ede2af0e99103efc 100644 (file)
--- a/system.v
+++ b/system.v
@@ -1,7 +1,15 @@
 `define BUS_ICACHE 1
 `define BUS_DCACHE 0
 
 `define BUS_ICACHE 1
 `define BUS_DCACHE 0
 

-module System(input clk);
+module System(input clk
+`ifdef verilator
+`else
+       , output wire [8:0] sys_odata,
+       input [8:0] sys_idata,
+       output wire sys_tookdata
+`endif
+       );
+       

        wire [7:0] bus_req;
        wire [7:0] bus_ack;
        wire [31:0] bus_addr;
        wire [7:0] bus_req;
        wire [7:0] bus_ack;
        wire [31:0] bus_addr;


@@ -208,7 +216,12 @@ module System(input clk);
        Terminal terminal(      
                .clk(clk),
                .cp_req(cp_req), .cp_insn(cp_insn), .cp_ack(cp_ack_terminal), .cp_busy(cp_busy_terminal), .cp_rnw(cp_rnw),
        Terminal terminal(      
                .clk(clk),
                .cp_req(cp_req), .cp_insn(cp_insn), .cp_ack(cp_ack_terminal), .cp_busy(cp_busy_terminal), .cp_rnw(cp_rnw),

-               .cp_read(cp_read_terminal), .cp_write(cp_write));
+               .cp_read(cp_read_terminal), .cp_write(cp_write)
+`ifdef verilator
+`else
+               , .sys_odata(sys_odata), .sys_tookdata(sys_tookdata), .sys_idata(sys_idata)
+`endif
+               );

        
        Writeback writeback(
                .clk(clk),
        
        Writeback writeback(
                .clk(clk),