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Memory: Only make the final latch for prev_reg and regs be gated on rw_wait.
authorJoshua Wise <joshua@rebirth.joshuawise.com>
Sat, 31 Jan 2009 10:49:31 +0000 (05:49 -0500)
committerJoshua Wise <joshua@rebirth.joshuawise.com>
Sat, 31 Jan 2009 10:49:31 +0000 (05:49 -0500)

No differences found
FireARM pipelined ARM-like CPU implementation in Verilog
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