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system: Swap ICache and DCache in arbiter order.
author
Joshua Wise
<joshua@rebirth.joshuawise.com>
Tue, 13 Jan 2009 08:40:57 +0000
(
03:40
-0500)
committer
Joshua Wise
<joshua@rebirth.joshuawise.com>
Tue, 13 Jan 2009 08:40:57 +0000
(
03:40
-0500)
system.v
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diff --git
a/system.v
b/system.v
index
602f4fd
..
1635a34
100644
(file)
--- a/
system.v
+++ b/
system.v
@@
-1,5
+1,5
@@
-`define BUS_ICACHE
0
-`define BUS_DCACHE
1
+`define BUS_ICACHE
1
+`define BUS_DCACHE
0
module System(input clk);
wire [7:0] bus_req;
module System(input clk);
wire [7:0] bus_req;
@@
-12,7
+12,7
@@
module System(input clk);
wire bus_req_icache;
wire bus_req_dcache;
wire bus_req_icache;
wire bus_req_dcache;
- assign bus_req = {6'b0, bus_req_
dcache, bus_req_i
cache};
+ assign bus_req = {6'b0, bus_req_
icache, bus_req_d
cache};
wire bus_ack_icache = bus_ack[`BUS_ICACHE];
wire bus_ack_dcache = bus_ack[`BUS_DCACHE];
wire bus_ack_icache = bus_ack[`BUS_ICACHE];
wire bus_ack_dcache = bus_ack[`BUS_DCACHE];
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