Issue: Use wires, since again XST can't always @(cpsr_inflight).
authorJoshua Wise <joshua@rebirth.joshuawise.com>
Sat, 24 Jan 2009 09:18:58 +0000 (04:18 -0500)
committerJoshua Wise <joshua@rebirth.joshuawise.com>
Sat, 24 Jan 2009 09:18:58 +0000 (04:18 -0500)
Issue.v

diff --git a/Issue.v b/Issue.v
index 792fdbd..153f25f 100644 (file)
--- a/Issue.v
+++ b/Issue.v
@@ -12,7 +12,7 @@ module Issue(
        input [31:0] inpc,
        input [31:0] cpsr,
        
-       output reg outstall = 0,        /* stage outputs */
+       output wire outstall,   /* stage outputs */
        output reg outbubble = 1,
        output reg [31:0] outpc = 0,
        output reg [31:0] outinsn = 0
@@ -265,10 +265,6 @@ module Issue(
        reg cpsr_inflight [1:0];
        reg [15:0] regs_inflight [1:0];
        
-       reg waiting_cpsr;
-       reg waiting_regs;
-       wire waiting = waiting_cpsr | waiting_regs;
-       
        initial
        begin
                cpsr_inflight[0] = 0;
@@ -276,14 +272,11 @@ module Issue(
                regs_inflight[0] = 0;
                regs_inflight[1] = 0;
        end
-               
-       always @(*)
-       begin
-               waiting_cpsr = use_cpsr & (cpsr_inflight[0] | cpsr_inflight[1]);
-               waiting_regs = |(use_regs & (regs_inflight[0] | regs_inflight[1]));
-               
-               outstall = (waiting && !inbubble && !flush) || stall;   /* Happens in an always @*, because it is an exception. */
-       end
+       
+       wire waiting_cpsr = use_cpsr & (cpsr_inflight[0] | cpsr_inflight[1]);
+       wire waiting_regs = |(use_regs & (regs_inflight[0] | regs_inflight[1]));
+       wire waiting = waiting_cpsr | waiting_regs;
+       assign outstall = (waiting && !inbubble && !flush) || stall;
 
        reg delayedflush = 0;
        always @(posedge clk)
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