Add special CPSR behavior for ARM MCR.

diff --git a/Memory.v b/Memory.v
index c735ed92af16303a5b5c75e3d1c60d716c5d16ca..ff9f397771df212f5719bdec695eda4c3e194fb4 100644 (file)
--- a/Memory.v
+++ b/Memory.v
@@ -325,9 +325,12 @@ module Memory(
                        if (insn[20] == 0 /* store to coprocessor */)
                                cp_write = op0;
                        else begin
                        if (insn[20] == 0 /* store to coprocessor */)
                                cp_write = op0;
                        else begin

-                               next_write_reg = 1'b1;
-                               next_write_num = insn[15:12];
-                               next_write_data = cp_read;
+                               if (insn[15:12] != 4'hF /* Fuck you ARM */) begin
+                                       next_write_reg = 1'b1;
+                                       next_write_num = insn[15:12];
+                                       next_write_data = cp_read;
+                               end else
+                                       next_outcpsr = {cp_read[31:28], cpsr[27:0]};

                        end
                        if (cp_busy) begin
                                outstall = 1;
                        end
                        if (cp_busy) begin
                                outstall = 1;