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Issue: Fix case in which lr is read in the instruction immediately after a bl; now...
authorJoshua Wise <joshua@rebirth.joshuawise.com>
Fri, 23 Jan 2009 09:58:39 +0000 (04:58 -0500)
committerJoshua Wise <joshua@rebirth.joshuawise.com>
Fri, 23 Jan 2009 09:58:39 +0000 (04:58 -0500)

No differences found
FireARM pipelined ARM-like CPU implementation in Verilog
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