Memory.v: Cleanup pass 1 before integration.

diff --git a/Memory.v b/Memory.v
index 409b282f3cad4cb34325201dfcbf5fe7421441a3..9c010e71d98e5fe215af482fbe2ce53f45036814 100644 (file)
--- a/Memory.v
+++ b/Memory.v
@@ -3,10 +3,6 @@
 module Memory(
        input clk,
        input Nrst,
 module Memory(
        input clk,
        input Nrst,

-       input [31:0] pc,
-       input [31:0] insn,
-       input [31:0] base,
-       input [31:0] offset,

 
        /* bus interface */
        output reg [31:0] busaddr,
 
        /* bus interface */
        output reg [31:0] busaddr,


@@ -19,28 +15,50 @@ module Memory(
        /* regfile interface */
        output reg [3:0] st_read,
        input [31:0] st_data,
        /* regfile interface */
        output reg [3:0] st_read,
        input [31:0] st_data,

+       
+       /* stage inputs */
+       input inbubble,
+       input [31:0] pc,
+       input [31:0] insn,
+       input [31:0] base,
+       input [31:0] offset,
+       input write_reg,
+       input [3:0] write_num,
+       input [31:0] write_data,

 
 

-       /* writeback to base */
-       output reg writeback,
-       output reg [3:0] regsel,
-       output reg [31:0] regdata,
-
-       /* pc stuff */
+       /* outputs */
+       output reg outstall,
+       output reg outbubble,

        output reg [31:0] outpc,
        output reg [31:0] outpc,

-
-       /* stall */
-       output outstall,
-       output reg outbubble
-);
+       output reg [31:0] outinsn,
+       output reg out_write_reg = 1'b0,
+       output reg [3:0] out_write_num = 4'bxxxx,
+       output reg [31:0] out_write_data = 32'hxxxxxxxx
+       );

 
        reg [31:0] addr, raddr, next_regdata;
        reg [3:0] next_regsel;
        reg next_writeback, next_notdone, next_inc_next;
        reg [31:0] align_s1, align_s2, align_rddata;
 
        reg [31:0] addr, raddr, next_regdata;
        reg [3:0] next_regsel;
        reg next_writeback, next_notdone, next_inc_next;
        reg [31:0] align_s1, align_s2, align_rddata;

+       
+       wire next_write_reg;
+       wire [3:0] next_write_num;
+       wire [31:0] next_write_data;

 
        reg notdone = 1'b0;
        reg inc_next = 1'b0;
 
        reg notdone = 1'b0;
        reg inc_next = 1'b0;

-       assign outstall = rw_wait | notdone;
+
+       always @(posedge clk)
+       begin
+               outpc <= pc;
+               outinsn <= insn;
+               outbubble <= rw_wait;
+               out_write_reg <= next_writeback;
+               out_write_num <= next_regsel;
+               out_write_data <= next_regdata;
+               notdone <= next_notdone;
+               inc_next <= next_inc_next;
+       end

 
        always @(*)
        begin
 
        always @(*)
        begin


@@ -52,57 +70,51 @@ module Memory(
                busaddr = 32'hxxxxxxxx;
                outstall = 1'b0;
                next_notdone = 1'b0;
                busaddr = 32'hxxxxxxxx;
                outstall = 1'b0;
                next_notdone = 1'b0;

-               next_regsel = 4'hx;
-               next_regdata = 32'hxxxxxxxx;
+               next_write_reg = write_reg;
+               next_write_num = write_num;
+               next_write_data = write_data;

                next_inc_next = 1'b0;
                next_inc_next = 1'b0;

+               outstall = 1'b0;
+               

                casez(insn)
                `DECODE_LDRSTR_UNDEFINED: begin end
                `DECODE_LDRSTR: begin
                casez(insn)
                `DECODE_LDRSTR_UNDEFINED: begin end
                `DECODE_LDRSTR: begin

-                       addr = insn[23] ? base + offset : base - offset; /* up/down select */
-                       raddr = insn[24] ? base : addr;
-                       busaddr = {raddr[31:2], 2'b0}; /* pre/post increment */
-                       rd_req = insn[20];
-                       wr_req = ~insn[20];
-
-                       /* rotate to correct position */
-                       align_s1 = raddr[1] ? {rd_data[15:0], rd_data[31:16]} : rd_data;
-                       align_s2 = raddr[0] ? {align_s1[7:0], align_s1[31:8]} : align_s1;
-                       /* select byte or word */
-                       align_rddata = insn[22] ? {24'b0, align_s2[7:0]} : align_s2;
-
-                       if(!insn[20]) begin
-                               st_read = insn[15:12];
-                               wr_data = insn[22] ? {4{st_data[7:0]}} : st_data; /* XXX need to actually store just a byte */
+                       if (!inbubble) begin
+                               outstall = rw_wait | notdone;
+                       
+                               addr = insn[23] ? base + offset : base - offset; /* up/down select */
+                               raddr = insn[24] ? base : addr;
+                               busaddr = {raddr[31:2], 2'b0}; /* pre/post increment */
+                               rd_req = insn[20];
+                               wr_req = ~insn[20];
+                               
+                               /* rotate to correct position */
+                               align_s1 = raddr[1] ? {rd_data[15:0], rd_data[31:16]} : rd_data;
+                               align_s2 = raddr[0] ? {align_s1[7:0], align_s1[31:8]} : align_s1;
+                               /* select byte or word */
+                               align_rddata = insn[22] ? {24'b0, align_s2[7:0]} : align_s2;
+                               
+                               if(!insn[20]) begin
+                                       st_read = insn[15:12];
+                                       wr_data = insn[22] ? {4{st_data[7:0]}} : st_data; /* XXX need to actually store just a byte */
+                               end
+                               else if(!inc_next) begin
+                                       next_write_reg = 1'b1;
+                                       next_write_num = insn[15:12];
+                                       next_write_data = align_rddata;
+                                       next_inc_next = 1'b1;
+                               end
+                               else if(insn[21]) begin
+                                       next_write_reg = 1'b1;
+                                       next_write_num = insn[19:16];
+                                       next_write_data = addr;
+                               end
+                               next_notdone = rw_wait & insn[20] & insn[21];

                        end
                        end

-                       else if(!inc_next) begin
-                               next_writeback = 1'b1;
-                               next_regsel = insn[15:12];
-                               next_regdata = align_rddata;
-                               next_inc_next = 1'b1;
-                       end
-                       else if(insn[21]) begin
-                               next_writeback = 1'b1;
-                               next_regsel = insn[19:16];
-                               next_regdata = addr;
-                       end
-                       next_notdone = rw_wait & insn[20] & insn[21];

                end
                `DECODE_LDMSTM: begin
                end
                default: begin end
                endcase
        end
                end
                `DECODE_LDMSTM: begin
                end
                default: begin end
                endcase
        end

-
-
-       always @(posedge clk)
-       begin
-               outpc <= pc;
-               outbubble <= rw_wait;
-               writeback <= next_writeback;
-               regsel <= next_regsel;
-               regdata <= next_regdata;
-               notdone <= next_notdone;
-               inc_next <= next_inc_next;
-       end
-

 endmodule
 endmodule