Initialize more things, and follow more clocking rules.

diff --git a/BlockRAM.v b/BlockRAM.v
index 85f865974fbd3f3bb88e13bb2d3cfe274d0b3607..cfb5d700bb0eb530b3aab887a6b10ac564baee48 100644 (file)
--- a/BlockRAM.v
+++ b/BlockRAM.v
@@ -18,15 +18,18 @@ module BlockRAM(
                                                         * for word alignment */
        /* verilator lint_on WIDTH */
        
                                                         * for word alignment */
        /* verilator lint_on WIDTH */
        

-       reg [31:0] data [0:(16384 / 4 - 1)];
+       reg [31:0] data [(16384 / 4 - 1):0];

        
        

-       reg [31:0] temprdata;
-       reg [13:2] lastread;
+       reg [31:0] temprdata = 0;
+       reg [13:2] lastread = 0;

        assign bus_rdata = (bus_rd && decode) ? temprdata : 32'h0;
        
        assign bus_ready = decode &&
                (bus_wr || (bus_rd && (lastread == ramaddr)));
        
        assign bus_rdata = (bus_rd && decode) ? temprdata : 32'h0;
        
        assign bus_ready = decode &&
                (bus_wr || (bus_rd && (lastread == ramaddr)));
        

+       initial
+               $readmemh("ram.hex", data);
+       

        always @(posedge clk)
        begin
                if (bus_wr && decode)
        always @(posedge clk)
        begin
                if (bus_wr && decode)

diff --git a/Fetch.v b/Fetch.v
index 0a18b31e6e9a4c68cc5b83112257e5ea58c1a7d2..3b6d9c57f9f5f090884e752ef0fdb68faa96263f 100644 (file)
--- a/Fetch.v
+++ b/Fetch.v
@@ -10,32 +10,39 @@ module Fetch(
        input stall,
        input jmp,
        input [31:0] jmppc,
        input stall,
        input jmp,
        input [31:0] jmppc,

-       output wire bubble,
-       output wire [31:0] insn,
-       output reg [31:0] pc);
+       output reg bubble = 1,
+       output reg [31:0] insn = 0,
+       output reg [31:0] pc = 0);

 
        reg [31:0] prevpc;
 
        reg [31:0] prevpc;

+       reg [31:0] nextpc;

        initial
                prevpc = 32'hFFFFFFFC;  /* ugh... the first pc we request will be this +4 */
        always @(negedge Nrst)
                prevpc <= 32'hFFFFFFFC;
        initial
                prevpc = 32'hFFFFFFFC;  /* ugh... the first pc we request will be this +4 */
        always @(negedge Nrst)
                prevpc <= 32'hFFFFFFFC;

-       
-       always @(*)
+
+       always @(*)     

                if (!Nrst)
                if (!Nrst)

-                       pc = 32'hFFFFFFFC;
+                       nextpc = 32'hFFFFFFFC;

                else if (stall) /* don't change any internal state */
                else if (stall) /* don't change any internal state */

-                       pc = prevpc;
+                       nextpc = prevpc;

                else if (jmp)
                else if (jmp)

-                       pc = jmppc;
+                       nextpc = jmppc;

                else
                else

-                       pc = prevpc + 32'h4;
+                       nextpc = prevpc + 32'h4;

        
        

-       assign bubble = stall | rd_wait;

        assign rd_addr = pc;
        assign rd_req = !stall;
        assign rd_addr = pc;
        assign rd_req = !stall;

-       assign insn = rd_data;

                        
        always @(posedge clk)
                        
        always @(posedge clk)

+       begin

                if (!rd_wait || !Nrst)
                if (!rd_wait || !Nrst)

-                       prevpc <= pc;
+                       prevpc <= nextpc;
+               if (!stall)
+               begin
+                       bubble <= rd_wait;
+                       insn <= rd_data;
+                       pc <= nextpc;
+               end
+       end

 endmodule
 endmodule

diff --git a/ICache.v b/ICache.v
index 3a9f14481be7a2cc9c92dcbd036d7193602cf9ae..43f60281abd93bc5850f147835ff09771ec0caa9 100644 (file)
--- a/ICache.v
+++ b/ICache.v
@@ -10,7 +10,7 @@ module ICache(
        output reg [31:0] rd_data,
        
        /* bus interface */
        output reg [31:0] rd_data,
        
        /* bus interface */

-       output reg bus_req,
+       output wire bus_req,

        input bus_ack,
        output reg [31:0] bus_addr,
        input [31:0] bus_rdata,
        input bus_ack,
        output reg [31:0] bus_addr,
        input [31:0] bus_rdata,


@@ -35,7 +35,10 @@ module ICache(
        reg [4:0] i;
        initial
                for (i = 0; i < 16; i = i + 1)
        reg [4:0] i;
        initial
                for (i = 0; i < 16; i = i + 1)

+               begin

                        cache_valid[i[3:0]] = 0;
                        cache_valid[i[3:0]] = 0;

+                       cache_tags[i[3:0]] = 0;
+               end

        
        wire [5:0] rd_didx = rd_addr[5:0];
        wire [3:0] rd_didx_word = rd_didx[5:2];
        
        wire [5:0] rd_didx = rd_addr[5:0];
        wire [3:0] rd_didx_word = rd_didx[5:2];

diff --git a/Issue.v b/Issue.v
index 6b25d3752a044e54e56f77c3c83d7acfc2b0e810..03707d9fa8bb8694cf0f261137bfdcce66a046c2 100644 (file)
--- a/Issue.v
+++ b/Issue.v
@@ -12,10 +12,10 @@ module Issue(
        input [31:0] inpc,
        input [31:0] cpsr,
        
        input [31:0] inpc,
        input [31:0] cpsr,
        

-       output reg outstall,    /* stage outputs */
-       output reg outbubble,
-       output reg [31:0] outpc,
-       output reg [31:0] outinsn
+       output reg outstall = 0,        /* stage outputs */
+       output reg outbubble = 1,
+       output reg [31:0] outpc = 0,
+       output reg [31:0] outinsn = 0

        /* XXX other? */
        );
        
        /* XXX other? */
        );
        


@@ -276,19 +276,20 @@ module Issue(
        begin
                waiting_cpsr = use_cpsr & (cpsr_inflight[0] | cpsr_inflight[1]);
                waiting_regs = |(use_regs & (regs_inflight[0] | regs_inflight[1]));
        begin
                waiting_cpsr = use_cpsr & (cpsr_inflight[0] | cpsr_inflight[1]);
                waiting_regs = |(use_regs & (regs_inflight[0] | regs_inflight[1]));

+               
+               outstall = waiting && !inbubble;        /* Happens in an always @*, because it is an exception. */

        end
        
        /* Actually do the issue. */
        always @(posedge clk)
        begin
                cpsr_inflight[0] <= cpsr_inflight[1];   /* I'm not sure how well selects work with arrays, and that seems like a dumb thing to get anusulated by. */
        end
        
        /* Actually do the issue. */
        always @(posedge clk)
        begin
                cpsr_inflight[0] <= cpsr_inflight[1];   /* I'm not sure how well selects work with arrays, and that seems like a dumb thing to get anusulated by. */

-               cpsr_inflight[1] <= ((waiting | inbubble) && condition_met) ? 0 : def_cpsr;
+               cpsr_inflight[1] <= (waiting || inbubble || !condition_met) ? 0 : def_cpsr;

                regs_inflight[0] <= regs_inflight[1];
                regs_inflight[0] <= regs_inflight[1];

-               regs_inflight[1] <= ((waiting | inbubble) && condition_met) ? 0 : def_regs;
+               regs_inflight[1] <= (waiting || inbubble || !condition_met) ? 0 : def_regs;

 
                outbubble <= inbubble | waiting | !condition_met;
                outpc <= inpc;
                outinsn <= insn;
 
                outbubble <= inbubble | waiting | !condition_met;
                outpc <= inpc;
                outinsn <= insn;

-               outstall <= waiting && !inbubble;

        end
 endmodule
        end
 endmodule

diff --git a/system.v b/system.v
index e33bbff1ede9eb05cfc1741006ce28a35b9e7169..afd7a177c989f80c058e83d3f1cfc51e04c7de10 100644 (file)
--- a/system.v
+++ b/system.v
@@ -84,4 +84,11 @@ module System(input clk, output wire bubbleshield, output wire [31:0] insn, outp
                .inpc(pc_out_fetch), .cpsr(0 /* XXX */),
                .outstall(stall_cause_issue), .outbubble(bubble_out_issue),
                .outpc(pc_out_issue), .outinsn(insn_out_issue));
                .inpc(pc_out_fetch), .cpsr(0 /* XXX */),
                .outstall(stall_cause_issue), .outbubble(bubble_out_issue),
                .outpc(pc_out_issue), .outinsn(insn_out_issue));

+       
+       always @(posedge clk)
+       begin
+               $display("Clock-time dump:");
+               $display("Fetch stage: Bubble output: %d, Instruction: %08x, PC: %08x", bubble_out_fetch, insn_out_fetch, pc_out_fetch);
+               $display("Issue stage: Stall output: %d, Bubble output: %d, Instruction: %08x, PC: %08x", stall_cause_issue, bubble_out_issue, insn_out_issue, pc_out_issue);
+       end

 endmodule
 endmodule