Initialize more things, and follow more clocking rules.
[firearm.git] / BlockRAM.v
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1module BlockRAM(
2 input clk,
3 input [31:0] bus_addr,
4 output wire [31:0] bus_rdata,
5 input [31:0] bus_wdata,
6 input bus_rd,
7 input bus_wr,
8 output wire bus_ready
9 );
10
11 /* This module is mapped in physical memory from 0x00000000 to
12 * 0x00004000. rdata and ready must be driven to zero if the
13 * address is not within the range of this module.
14 */
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15 wire decode = (bus_addr & ~32'h00003FFF) == 32'h00000000;
16 /* verilator lint_off WIDTH */
17 wire [13:2] ramaddr = bus_addr & 32'h3FFC; /* mask off lower two bits
18 * for word alignment */
19 /* verilator lint_on WIDTH */
2f8f0594 20
90ff449a 21 reg [31:0] data [(16384 / 4 - 1):0];
2f8f0594 22
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23 reg [31:0] temprdata = 0;
24 reg [13:2] lastread = 0;
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25 assign bus_rdata = (bus_rd && decode) ? temprdata : 32'h0;
26
27 assign bus_ready = decode &&
28 (bus_wr || (bus_rd && (lastread == ramaddr)));
29
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30 initial
31 $readmemh("ram.hex", data);
32
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33 always @(posedge clk)
34 begin
35 if (bus_wr && decode)
36 data[ramaddr] <= bus_wdata;
37
38 /* This is not allowed to be conditional -- stupid Xilinx
39 * blockram. */
40 temprdata <= data[ramaddr];
41 lastread <= ramaddr;
42 end
43endmodule
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