Execute: most of an ALU, ARM_Constants: RBC -> RSC

diff --git a/ARM_Constants.v b/ARM_Constants.v
index 2eedd3abe862a7a62d1d6571a636842277f0a921..04dd4dd64efdad96b983222fce61eaa4c4de2d93 100644 (file)
--- a/ARM_Constants.v
+++ b/ARM_Constants.v
@@ -24,7 +24,7 @@
 `define ALU_ADD 4'b0100
 `define ALU_ADC 4'b0101
 `define ALU_SBC 4'b0110
-`define ALU_RBC 4'b0111
+`define ALU_RSC 4'b0111
 `define ALU_TST 4'b1000
 `define ALU_TEQ 4'b1001
 `define ALU_CMP 4'b1010

diff --git a/Execute.v b/Execute.v
index d7b4ba6485036b666a5cee9b6c6d0309870c035f..4865aa359bd262ceabc18a21bcae8e098698fcfe 100644 (file)
--- a/Execute.v
+++ b/Execute.v
@@ -68,3 +68,122 @@ module Multiplier(
                end
        end
 endmodule
+
+/* XXX is the interface correct? */
+module ALU(
+       input clk,
+       input Nrst,     /* XXX not used yet */
+
+       input [31:0] in0,
+       input [31:0] in1,
+       input [31:0] cpsr,
+       input [3:0] op,
+       input setflags,
+       input shifter_carry,
+
+       output reg [31:0] result,
+       output reg [31:0] cpsr_out,
+       output reg set
+);
+       wire [31:0] res;
+       wire flag_n, flag_z, flag_c, flag_v, setres;
+       wire [32:0] sum, diff, rdiff;
+
+       assign sum = {1'b0, in0} + {1'b0, in1};
+       assign diff = {1'b0, in0} - {1'b0, in1};
+       assign rdiff = {1'b0, in1} + {1'b0, in0};
+
+       /* TODO XXX flag_v not set correctly */
+       always @(*) begin
+               res = 32'hxxxxxxxx;
+               setres = 1'bx;
+               flag_c = cpsr[`CPSR_C];
+               flag_v = cpsr[`CPSR_V];
+               case(op)
+               `ALU_AND: begin
+                       res = in0 & in1;
+                       flag_c = shifter_carry;
+                       setres = 1'b1;
+               end
+               `ALU_EOR: begin
+                       res = in0 ^ in1;
+                       flag_c = shifter_carry;
+                       setres = 1'b1;
+               end
+               `ALU_SUB: begin
+                       {flag_c, res} = diff;
+                       setres = 1'b1;
+               end
+               `ALU_RSB: begin
+                       {flag_c, res} = rdiff;
+                       setres = 1'b1;
+               end
+               `ALU_ADD: begin
+                       {flag_c, res} = sum;
+                       setres = 1'b1;
+               end
+               `ALU_ADC: begin
+                       {flag_c, res} = sum + cpsr[`CPSR_C];
+                       setres = 1'b1;
+               end
+               `ALU_SBC: begin
+                       {flag_c, res} = diff - (~cpsr[`CPSR_C]);
+                       setres = 1'b1;
+               end
+               `ALU_RSC: begin
+                       {flag_c, res} = rdiff - (~cpsr[`CPSR_C]);
+                       setres = 1'b1;
+               end
+               `ALU_TST: begin
+                       res = in0 & in1;
+                       flag_c = shifter_carry;
+                       setres = 1'b0;
+               end
+               `ALU_TEQ: begin
+                       res = in0 ^ in1;
+                       flag_c = shifter_carry;
+                       setres = 1'b0;
+               end
+               `ALU_CMP: begin
+                       {flag_c, res} = diff;
+                       setres = 1'b0;
+               end
+               `ALU_CMN: begin
+                       {flag_c, res} = sum;
+                       setres = 1'b0;
+               end
+               `ALU_ORR: begin
+                       res = in0 | in1;
+                       flag_c = shifter_carry;
+                       setres = 1'b1;
+               end
+               `ALU_MOV: begin
+                       res = in1;
+                       flag_c = shifter_carry;
+                       setres = 1'b1;
+               end
+               `ALU_BIC: begin
+                       res = in0 & (~in1);
+                       flag_c = shifter_carry;
+                       setres = 1'b1;
+               end
+               `ALU_MVN: begin
+                       res = ~in1;
+                       flag_c = shifter_carry;
+                       setres = 1'b1;
+               end
+               endcase
+       end
+
+       always @(*) begin
+               flag_z = (res == 0);
+               flag_n = res[31];
+       end
+
+       always @(posedge clk) begin
+               result <= res;
+               cpsr_out <= setflags ? {flag_n, flag_z, flag_c, flag_v, cpsr[27:0]} : cpsr;
+               set <= setres;
+       end
+
+endmodule