Commit flag setter for issue.

diff --git a/ARM_Constants.v b/ARM_Constants.v
index c8c0f1e8624489088fedb46077724fdcec02c2c7..921e6eca747d1fd630315b7eeb0c7adf1162c344 100644 (file)
--- a/ARM_Constants.v
+++ b/ARM_Constants.v
@@ -8,7 +8,7 @@
 `define COND_VC 4'b0111        /* V clear */
 `define COND_HI 4'b1000        /* C set and Z clear */
 `define COND_LS 4'b1001        /* C clear or Z set */
 `define COND_VC 4'b0111        /* V clear */
 `define COND_HI 4'b1000        /* C set and Z clear */
 `define COND_LS 4'b1001        /* C clear or Z set */

-`define COND_GT 4'b1010        /* N equal to V */
+`define COND_GE 4'b1010        /* N equal to V */

 `define COND_LT 4'b1011        /* N not equal to V */
 `define COND_GT 4'b1100 /* Z clear AND (N equals V) */
 `define COND_LE 4'b1101        /* Z set OR (N not equals V) */
 `define COND_LT 4'b1011        /* N not equal to V */
 `define COND_GT 4'b1100 /* Z clear AND (N equals V) */
 `define COND_LE 4'b1101        /* Z set OR (N not equals V) */


@@ -33,3 +33,8 @@
 `define ALU_MOV 4'b1101
 `define ALU_BIC 4'b1110
 `define ALU_MVN 4'b1111
 `define ALU_MOV 4'b1101
 `define ALU_BIC 4'b1110
 `define ALU_MVN 4'b1111

+
+`define SHIFT_LSL 2'b00
+`define SHIFT_LSR 2'b01
+`define SHIFT_ASR 2'b10
+`define SHIFT_ROR 2'b11
\ No newline at end of file

diff --git a/Issue.v b/Issue.v
index 81038176bd5eeef5a8f82e1af71fbdfef62e68d5..a450190c28faa0b7926995e60d90d42adff71438 100644 (file)
--- a/Issue.v
+++ b/Issue.v
@@ -1,3 +1,5 @@
+`include "ARM_Constants.v"
+

 module Issue(
        input clk,
        input Nrst,
 module Issue(
        input clk,
        input Nrst,


@@ -45,7 +47,6 @@ module Issue(
        endcase
 `endif
 
        endcase
 `endif
 

-`ifdef WIP

        /* Flag setting */
        reg use_cpsr;
        reg [15:0] use_regs;
        /* Flag setting */
        reg use_cpsr;
        reg [15:0] use_regs;


@@ -54,11 +55,15 @@ module Issue(
        
        function [15:0] idxbit;
                input [3:0] r;
        
        function [15:0] idxbit;
                input [3:0] r;

-               idxbit = (16'b1) << r;
+               if (r == 15)
+                       idxbit = 0;
+               else
+                       idxbit = (16'b1) << r;

        endfunction
        
        wire [3:0] rn = insn[19:16];
        wire [3:0] rd = insn[15:12];
        endfunction
        
        wire [3:0] rn = insn[19:16];
        wire [3:0] rd = insn[15:12];

+       wire [3:0] rs = insn[11:8];

        wire [3:0] rm = insn[3:0];
        wire [3:0] cond = insn[31:28];
        
        wire [3:0] rm = insn[3:0];
        wire [3:0] cond = insn[31:28];
        


@@ -66,8 +71,39 @@ module Issue(
        wire [3:0] rn_mul = insn[15:12];
        wire [3:0] rs_mul = insn[11:8];
        
        wire [3:0] rn_mul = insn[15:12];
        wire [3:0] rs_mul = insn[11:8];
        

+       wire [3:0] alu_opc = insn[24:21];
+       
+       function alu_is_logical;
+               input [3:0] op;
+               
+               case (op)
+               `ALU_AND,`ALU_EOR,`ALU_TST,`ALU_TEQ,`ALU_ORR,`ALU_MOV,`ALU_BIC,`ALU_MVN: alu_is_logical = 1;
+               default: alu_is_logical = 0;
+               endcase
+       endfunction
+       
+       function alu_flags_only;
+               input [3:0] op;
+               
+               case (op)
+               `ALU_TST,`ALU_TEQ,`ALU_CMP,`ALU_CMN: alu_flags_only = 1;
+               default: alu_flags_only = 0;
+               endcase
+       endfunction
+       
+       function shift_requires_carry;
+               input [7:0] shift;
+               
+               case(shift[1:0])
+               `SHIFT_LSL: shift_requires_carry = (shift[7:2] == 0);
+               `SHIFT_LSR: shift_requires_carry = 0;
+               `SHIFT_ASR: shift_requires_carry = 0;
+               `SHIFT_ROR: shift_requires_carry = (shift[7:2] == 0);
+               endcase
+       endfunction
+       

        always @(*)
        always @(*)

-               casex (insn)
+               casez (insn)

                32'b????000000??????????????1001????:   /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
                begin
                        use_cpsr = `COND_MATTERS(cond);
                32'b????000000??????????????1001????:   /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
                begin
                        use_cpsr = `COND_MATTERS(cond);


@@ -77,22 +113,121 @@ module Issue(
                end
 //             32'b????00001???????????????1001????:   /* Multiply long */
                32'b????00010?001111????000000000000:   /* MRS (Transfer PSR to register) */
                end
 //             32'b????00001???????????????1001????:   /* Multiply long */
                32'b????00010?001111????000000000000:   /* MRS (Transfer PSR to register) */

+               begin
+                       use_cpsr = `COND_MATTERS(cond) || (insn[22] == 0) /* Source = CPSR */;
+                       use_regs = 0;
+                       def_cpsr = 0;
+                       def_regs = idxbit(rd);
+               end

                32'b????00010?101001111100000000????:   /* MSR (Transfer register to PSR) */
                32'b????00010?101001111100000000????:   /* MSR (Transfer register to PSR) */

+               begin
+                       use_cpsr = `COND_MATTERS(cond);
+                       use_regs = idxbit(rm);
+                       def_cpsr = 1;
+                       def_regs = 0;
+               end

                32'b????00?10?1010001111????????????:   /* MSR (Transfer register or immediate to PSR, flag bits only) */
                32'b????00?10?1010001111????????????:   /* MSR (Transfer register or immediate to PSR, flag bits only) */

+               begin
+                       use_cpsr = `COND_MATTERS(cond);
+                       use_regs = insn[25] ? 0 : idxbit(rm);
+                       def_cpsr = 1;
+                       def_regs = 0;
+               end

                32'b????00??????????????????????????:   /* ALU */
                32'b????00??????????????????????????:   /* ALU */

+               begin
+                       use_cpsr = `COND_MATTERS(cond) | (!insn[25] /* I */ && shift_requires_carry(insn[11:4]));
+                       use_regs =
+                               (insn[25] /* I */ ? 0 :
+                                       (insn[4] /* shift by reg */ ?
+                                               (idxbit(rs) | idxbit(rm)) :
+                                               (idxbit(rm)))) |
+                               (((alu_opc != `ALU_MOV) && (alu_opc != `ALU_MVN)) ? idxbit(rn) : 0);
+                       def_cpsr = insn[20] /* S */ | alu_is_logical(alu_opc);
+                       def_regs = alu_flags_only(alu_opc) ? 0 : idxbit(rd);
+               end

                32'b????00010?00????????00001001????:   /* Atomic swap */
                32'b????00010?00????????00001001????:   /* Atomic swap */

+               begin
+                       use_cpsr = `COND_MATTERS(cond);
+                       use_regs = idxbit(rn) | idxbit(rm);
+                       def_cpsr = 0;
+                       def_regs = idxbit(rd);
+               end

                32'b????000100101111111111110001????:   /* Branch */
                32'b????000100101111111111110001????:   /* Branch */

+               begin
+                       use_cpsr = `COND_MATTERS(cond);
+                       use_regs = idxbit(rm);
+                       def_cpsr = 0;   // don't care, we'll never get there
+                       def_regs = 0;
+               end

                32'b????000??0??????????00001??1????:   /* Halfword transfer - register offset */
                32'b????000??0??????????00001??1????:   /* Halfword transfer - register offset */

-               32'b????000??1??????????00001??1????:   /* Halfword transfer - register offset */
+               begin
+                       use_cpsr = `COND_MATTERS(cond);
+                       use_regs = idxbit(rn) | idxbit(rm) | (insn[20] /* L */ ? 0 : idxbit(rd));
+                       def_cpsr = 0;
+                       def_regs = insn[20] /* L */ ? idxbit(rd) : 0;
+               end
+               32'b????000??1??????????00001??1????:   /* Halfword transfer - immediate offset */
+               begin
+                       use_cpsr = `COND_MATTERS(cond);
+                       use_regs = idxbit(rn) | (insn[20] /* L */ ? 0 : idxbit(rd));
+                       def_cpsr = 0;
+                       def_regs = insn[20] /* L */ ? idxbit(rd) : 0;
+               end

                32'b????011????????????????????1????:   /* Undefined. I hate ARM */
                32'b????011????????????????????1????:   /* Undefined. I hate ARM */

-               32'b????01??????????????????????????:   /* Single data transfer */
+               begin   
+                       use_cpsr = 0;
+                       use_regs = 0;
+                       def_cpsr = 0;
+                       def_regs = 0;
+               end

                32'b????100?????????????????????????:   /* Block data transfer */
                32'b????100?????????????????????????:   /* Block data transfer */

+               begin
+                       use_cpsr = `COND_MATTERS(cond);
+                       use_regs = idxbit(rn) | (insn[20] /* L */ ? 0 : insn[15:0]);
+                       def_cpsr = insn[22];    /* This is a superset of all cases, anyway. */
+                       def_regs = (insn[21] /* W */ ? idxbit(rn) : 0) | (insn[20] /* L */ ? insn[15:0] : 0);
+               end

                32'b????101?????????????????????????:   /* Branch */
                32'b????101?????????????????????????:   /* Branch */

+               begin
+                       use_cpsr = `COND_MATTERS(cond);
+                       use_regs = 0;
+                       def_cpsr = 0;
+                       def_regs = 0;
+               end

                32'b????110?????????????????????????:   /* Coprocessor data transfer */
                32'b????110?????????????????????????:   /* Coprocessor data transfer */

+               begin
+                       use_cpsr = `COND_MATTERS(cond);
+                       use_regs = idxbit(rn);
+                       def_cpsr = 0;
+                       def_regs = insn[21] /* W */ ? idxbit(rn) : 0;
+               end

                32'b????1110???????????????????0????:   /* Coprocessor data op */
                32'b????1110???????????????????0????:   /* Coprocessor data op */

+               begin
+                       use_cpsr = `COND_MATTERS(cond);
+                       use_regs = 0;
+                       def_cpsr = 0;
+                       def_regs = 0;
+               end

                32'b????1110???????????????????1????:   /* Coprocessor register transfer */
                32'b????1110???????????????????1????:   /* Coprocessor register transfer */

+               begin
+                       use_cpsr = `COND_MATTERS(cond);
+                       use_regs = insn[20] /* L */ ? 0 : idxbit(rd);
+                       def_cpsr = 0;
+                       def_regs = insn[20] /* L */ ? idxbit(rd) : 0;
+               end

                32'b????1111????????????????????????:   /* SWI */
                32'b????1111????????????????????????:   /* SWI */

+               begin
+                       use_cpsr = `COND_MATTERS(cond);
+                       use_regs = 0;
+                       def_cpsr = 0;
+                       def_regs = 0;
+               end

                default:                                /* X everything else out */
                default:                                /* X everything else out */

+               begin
+                       use_cpsr = 1'bx;
+                       use_regs = 16'bxxxxxxxxxxxxxxxx;
+                       def_cpsr = 1'bx;
+                       def_regs = 16'bxxxxxxxxxxxxxxxx;
+               end

                endcase
                endcase

-`endif

 endmodule
 endmodule