st_data -> op2

diff --git a/Decode.v b/Decode.v
index a34eb3bce91f510b774707dec4c99aacfd75b883..b58951abff823e5070d6c043d875438884c24502 100644 (file)
--- a/Decode.v
+++ b/Decode.v
@@ -171,6 +171,7 @@ module Decode(
                begin
                        read_0 = insn[19:16]; /* Rn */
                        read_1 = insn[3:0];   /* Rm */
                begin
                        read_0 = insn[19:16]; /* Rn */
                        read_1 = insn[3:0];   /* Rm */

+                       read_2 = insn[15:12];

                        
                        op0_out = regs0;
                        if(insn[25]) begin
                        
                        op0_out = regs0;
                        if(insn[25]) begin


@@ -180,6 +181,7 @@ module Decode(
                                op1_out = shift_res;
                                carry_out = shift_cflag_out;
                        end
                                op1_out = shift_res;
                                carry_out = shift_cflag_out;
                        end

+                       op2_out = regs2;

                end
                `DECODE_LDMSTM:         /* Block data transfer */
                begin
                end
                `DECODE_LDMSTM:         /* Block data transfer */
                begin

diff --git a/Memory.v b/Memory.v
index 4af216d69711924dcc0ccd8fc47f841eb1abed15..237817790431c5f164bc0f4aadf9713b2fd08f27 100644 (file)
--- a/Memory.v
+++ b/Memory.v
@@ -22,6 +22,7 @@ module Memory(
        input [31:0] insn,
        input [31:0] op0,
        input [31:0] op1,
        input [31:0] insn,
        input [31:0] op0,
        input [31:0] op1,

+       input [31:0] op2,

        input write_reg,
        input [3:0] write_num,
        input [31:0] write_data,
        input write_reg,
        input [3:0] write_num,
        input [31:0] write_data,


@@ -98,8 +99,7 @@ module Memory(
                                align_rddata = insn[22] ? {24'b0, align_s2[7:0]} : align_s2;
                                
                                if(!insn[20]) begin
                                align_rddata = insn[22] ? {24'b0, align_s2[7:0]} : align_s2;
                                
                                if(!insn[20]) begin

-                                       st_read = insn[15:12];
-                                       wr_data = insn[22] ? {4{st_data[7:0]}} : st_data; /* XXX need to actually store just a byte */
+                                       wr_data = insn[22] ? {4{op2[7:0]}} : op2; /* XXX need to actually store just a byte */

                                end
                                else if(!inc_next) begin
                                        next_write_reg = 1'b1;
                                end
                                else if(!inc_next) begin
                                        next_write_reg = 1'b1;