DCache: Add instrumentation.

diff --git a/DCache.v b/DCache.v
index 472e1279df886e938d4ae77f2b24ab44ba22c2e8..098d9e8d4ad0f39089457bb706dd2fc8ca4d4e11 100644 (file)
--- a/DCache.v
+++ b/DCache.v
@@ -51,6 +51,8 @@ module DCache(
        always @(*) begin
                rw_wait = (rd_req && !cache_hit) || (wr_req && (!bus_ack || !bus_ready));
                rd_data = cache_data[idx][didx_word];
        always @(*) begin
                rw_wait = (rd_req && !cache_hit) || (wr_req && (!bus_ack || !bus_ready));
                rd_data = cache_data[idx][didx_word];

+               if (!rw_wait)
+                       $display("DCACHE: READ COMPLETE: Addr %08x, data %08x", addr, rd_data);

        end
        
        reg [3:0] cache_fill_pos = 0;
        end
        
        reg [3:0] cache_fill_pos = 0;


@@ -65,6 +67,7 @@ module DCache(
                        bus_addr = {addr[31:6], cache_fill_pos[3:0], 2'b00 /* reads are 32-bits */};
                        bus_rd = 1;
                end else if (wr_req && bus_ack) begin
                        bus_addr = {addr[31:6], cache_fill_pos[3:0], 2'b00 /* reads are 32-bits */};
                        bus_rd = 1;
                end else if (wr_req && bus_ack) begin

+                       $display("DCACHE: WRITE REQUEST: Addr %08x, data %08x", addr, wr_data);

                        bus_addr = addr;
                        bus_wr = 1;
                        bus_wdata = wr_data;
                        bus_addr = addr;
                        bus_wr = 1;
                        bus_wdata = wr_data;