module Fetch(
- input clk,
- input Nrst,
+ input clk,
+ input Nrst,
- output wire [31:0] rd_addr,
- output wire rd_req,
- input rd_wait,
- input [31:0] rd_data,
+ output wire [31:0] ic__rd_addr_0a,
+ output wire ic__rd_req_0a,
+ input ic__rd_wait_0a,
+ input [31:0] ic__rd_data_0a,
- input stall,
- input jmp,
- input [31:0] jmppc,
- output reg bubble = 1,
- output reg [31:0] insn = 0,
- output reg [31:0] pc = 32'hFFFFFFFC);
+ input stall_0a,
+ input jmp_0a,
+ input [31:0] jmppc_0a,
+ output reg bubble_1a = 1,
+ output reg [31:0] insn_1a = 0,
+ output reg [31:0] pc_1a = 32'hFFFFFFFC);
reg qjmp = 0; /* A jump has been queued up while we were waiting. */
reg [31:0] qjmppc;
always @(posedge clk or negedge Nrst)
if (!Nrst)
qjmp <= 0;
- else if ((rd_wait || stall) && jmp)
- {qjmp,qjmppc} <= {jmp, jmppc};
- else if (!rd_wait && !stall && qjmp) /* It has already been intoed. */
+ else if ((ic__rd_wait_0a || stall_0a) && jmp_0a)
+ {qjmp,qjmppc} <= {jmp_0a, jmppc_0a};
+ else if (!ic__rd_wait_0a && !stall_0a && qjmp) /* It has already been intoed. */
{qjmp,qjmppc} <= {1'b0, 32'hxxxxxxxx};
- reg [31:0] reqpc;
+ reg [31:0] reqpc_0a;
/* Output latch logic */
- assign rd_addr = reqpc;
- assign rd_req = 1;
+ assign ic__rd_addr_0a = reqpc_0a;
+ assign ic__rd_req_0a = 1;
always @(posedge clk or negedge Nrst)
if (!Nrst) begin
- bubble <= 1;
- insn <= 0;
- pc <= 32'h00000000;
- end else if (!stall) begin
- bubble <= (jmp || qjmp || rd_wait);
- insn <= rd_data;
- pc <= reqpc;
+ bubble_1a <= 1;
+ insn_1a <= 32'h00000000;
+ pc_1a <= 32'h00000000;
+ end else if (!stall_0a) begin
+ bubble_1a <= (jmp_0a || qjmp || ic__rd_wait_0a);
+ insn_1a <= ic__rd_data_0a;
+ pc_1a <= reqpc_0a;
end
always @(posedge clk or negedge Nrst)
if (!Nrst)
- reqpc <= 0;
- else if (!stall && !rd_wait) begin
+ reqpc_0a <= 0;
+ else if (!stall_0a && !ic__rd_wait_0a) begin
if (qjmp)
- reqpc <= qjmppc;
- else if (jmp)
- reqpc <= jmppc;
+ reqpc_0a <= qjmppc;
+ else if (jmp_0a)
+ reqpc_0a <= jmppc_0a;
else
- reqpc <= reqpc + 4;
+ reqpc_0a <= reqpc_0a + 4;
end
endmodule
input clk,
/* ARM core interface */
- input [31:0] rd_addr,
- input rd_req,
- output reg rd_wait,
- output reg [31:0] rd_data,
+ input [31:0] ic__rd_addr_0a,
+ input ic__rd_req_0a,
+ output wire ic__rd_wait_0a,
+ output wire [31:0] ic__rd_data_0a,
/* bus interface */
output wire bus_req,
assign bus_wr = 0;
assign bus_wdata = 0;
+ wire [31:0] rd_addr_0a;
+ wire rd_req_0a;
+ reg rd_wait_0a;
+ reg [31:0] rd_data_0a;
+ assign ic__rd_wait_0a = rd_wait_0a;
+ assign ic__rd_data_0a = rd_data_0a;
+ assign rd_addr_0a = ic__rd_addr_0a;
+ assign rd_req_0a = ic__rd_req_0a;
+
/* [31 tag 10] [9 cache index 6] [5 data index 0]
* so the data index is 6 bits long
* so the cache index is 4 bits long
cache_tags[i[3:0]] = 0;
end
- wire [5:0] rd_didx = rd_addr[5:0];
+ wire [5:0] rd_didx = rd_addr_0a[5:0];
wire [3:0] rd_didx_word = rd_didx[5:2];
- wire [3:0] rd_idx = rd_addr[9:6];
- wire [21:0] rd_tag = rd_addr[31:10];
+ wire [3:0] rd_idx = rd_addr_0a[9:6];
+ wire [21:0] rd_tag = rd_addr_0a[31:10];
reg [31:0] prev_rd_addr = 32'hFFFFFFFF;
wire cache_hit = cache_valid[rd_idx] && (cache_tags[rd_idx] == rd_tag);
reg [3:0] cache_fill_pos = 0;
- assign bus_req = rd_req && !cache_hit; /* xxx, needed for Verilator */
+ assign bus_req = rd_req_0a && !cache_hit; /* xxx, needed for Verilator */
always @(*)
- if (rd_req && !cache_hit && bus_ack) begin
- bus_addr = {rd_addr[31:6], cache_fill_pos[3:0], 2'b00 /* reads are 32-bits */};
+ if (rd_req_0a && !cache_hit && bus_ack) begin
+ bus_addr = {rd_addr_0a[31:6], cache_fill_pos[3:0], 2'b00 /* reads are 32-bits */};
bus_rd = 1;
end else begin
bus_addr = 0;
wire [31:0] curdata = cache_data[{rd_idx,rd_didx_word}];
always @(*) begin
- rd_wait = rd_req && !cache_hit;
- rd_data = curdata;
+ rd_wait_0a = rd_req_0a && !cache_hit;
+ rd_data_0a = curdata;
end
always @(posedge clk) begin
- prev_rd_addr <= {rd_addr[31:6], 6'b0};
- if (cache_fill_pos != 0 && ((prev_rd_addr != {rd_addr[31:6], 6'b0}) || cache_hit)) /* If this wasn't from the same line, or we've moved on somehow, reset the fill circuitry. */
+ prev_rd_addr <= {rd_addr_0a[31:6], 6'b0};
+ if (cache_fill_pos != 0 && ((prev_rd_addr != {rd_addr_0a[31:6], 6'b0}) || cache_hit)) /* If this wasn't from the same line, or we've moved on somehow, reset the fill circuitry. */
cache_fill_pos <= 0;
- else if (rd_req && !cache_hit && bus_ack && bus_ready) begin
- $display("ICACHE: FILL: rd addr %08x; bus addr %08x; bus data %08x", rd_addr, bus_addr, bus_rdata);
+ else if (rd_req_0a && !cache_hit && bus_ack && bus_ready) begin
+ $display("ICACHE: FILL: rd addr %08x; bus addr %08x; bus data %08x", rd_addr_0a, bus_addr, bus_rdata);
cache_data[{rd_idx,cache_fill_pos}] <= bus_rdata;
cache_fill_pos <= cache_fill_pos + 1;
if (cache_fill_pos == 15) begin /* Done? */
wire [31:0] pc_out_issue;
wire [31:0] pc_out_execute;
wire [31:0] pc_out_memory;
+
+ /*AUTOWIRE*/
+ // Beginning of automatic wires (for undeclared instantiated-module outputs)
+ wire [31:0] ic__rd_addr_0a; // From fetch of Fetch.v
+ wire [31:0] ic__rd_data_0a; // From icache of ICache.v
+ wire ic__rd_req_0a; // From fetch of Fetch.v
+ wire ic__rd_wait_0a; // From icache of ICache.v
+ // End of automatics
wire execute_out_backflush;
wire writeback_out_backflush;
BusArbiter busarbiter(.bus_req(bus_req), .bus_ack(bus_ack));
- ICache icache(
+ /* XXX reset? */
+ /* ICache AUTO_TEMPLATE (
.clk(clk),
- /* XXX reset? */
- .rd_addr(icache_rd_addr), .rd_req(icache_rd_req),
- .rd_wait(icache_rd_wait), .rd_data(icache_rd_data),
- .bus_req(bus_req_icache), .bus_ack(bus_ack_icache),
- .bus_addr(bus_addr_icache), .bus_rdata(bus_rdata),
- .bus_wdata(bus_wdata_icache), .bus_rd(bus_rd_icache),
- .bus_wr(bus_wr_icache), .bus_ready(bus_ready));
+ .bus_req(bus_req_icache),
+ .bus_ack(bus_ack_icache),
+ .bus_addr(bus_addr_icache),
+ .bus_rdata(bus_rdata),
+ .bus_wdata(bus_wdata_icache),
+ .bus_rd(bus_rd_icache),
+ .bus_wr(bus_wr_icache),
+ .bus_ready(bus_ready),
+ ); */
+ ICache icache(/*AUTOINST*/
+ // Outputs
+ .ic__rd_wait_0a (ic__rd_wait_0a),
+ .ic__rd_data_0a (ic__rd_data_0a[31:0]),
+ .bus_req (bus_req_icache), // Templated
+ .bus_addr (bus_addr_icache), // Templated
+ .bus_wdata (bus_wdata_icache), // Templated
+ .bus_rd (bus_rd_icache), // Templated
+ .bus_wr (bus_wr_icache), // Templated
+ // Inputs
+ .clk (clk), // Templated
+ .ic__rd_addr_0a (ic__rd_addr_0a[31:0]),
+ .ic__rd_req_0a (ic__rd_req_0a),
+ .bus_ack (bus_ack_icache), // Templated
+ .bus_rdata (bus_rdata), // Templated
+ .bus_ready (bus_ready)); // Templated
DCache dcache(
.clk(clk),
.bus_wdata(bus_wdata), .bus_rd(bus_rd), .bus_wr(bus_wr),
.bus_ready(bus_ready_blockram));
- Fetch fetch(
+ /* Fetch AUTO_TEMPLATE (
.clk(clk),
.Nrst(~rst),
- .rd_addr(icache_rd_addr), .rd_req(icache_rd_req),
- .rd_wait(icache_rd_wait), .rd_data(icache_rd_data),
- .stall(stall_cause_issue), .jmp(jmp), .jmppc(jmppc),
- .bubble(bubble_out_fetch), .insn(insn_out_fetch),
- .pc(pc_out_fetch));
+ .stall_0a(stall_cause_issue),
+ .jmp_0a(jmp),
+ .jmppc_0a(jmppc),
+ .bubble_1a(bubble_out_fetch),
+ .insn_1a(insn_out_fetch),
+ .pc_1a(pc_out_fetch),
+ );
+ */
+ Fetch fetch(
+ /*AUTOINST*/
+ // Outputs
+ .ic__rd_addr_0a (ic__rd_addr_0a[31:0]),
+ .ic__rd_req_0a (ic__rd_req_0a),
+ .bubble_1a (bubble_out_fetch), // Templated
+ .insn_1a (insn_out_fetch), // Templated
+ .pc_1a (pc_out_fetch), // Templated
+ // Inputs
+ .clk (clk), // Templated
+ .Nrst (~rst), // Templated
+ .ic__rd_wait_0a (ic__rd_wait_0a),
+ .ic__rd_data_0a (ic__rd_data_0a[31:0]),
+ .stall_0a (stall_cause_issue), // Templated
+ .jmp_0a (jmp), // Templated
+ .jmppc_0a (jmppc)); // Templated
Issue issue(
.clk(clk),
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