Wire things up, and fix circular logic in issue.

diff --git a/Issue.v b/Issue.v
index a7456568c77d0e013d56e1ddf06217f97c321944..628ef0886c193e420ba7f631cd0b5bf7bae2bec9 100644 (file)
--- a/Issue.v
+++ b/Issue.v
@@ -2,7 +2,7 @@
 
 module Issue(
        input clk,
-       input Nrst,
+       input Nrst,     /* XXX not used yet */
        
        input stall,    /* pipeline control */
        input flush,
@@ -271,19 +271,16 @@ module Issue(
        end
        
        /* Actually do the issue. */
-       always @(*)
-               outstall = waiting;
-       
        always @(posedge clk)
        begin
                cpsr_inflight[0] <= cpsr_inflight[1];   /* I'm not sure how well selects work with arrays, and that seems like a dumb thing to get anusulated by. */
-               cpsr_inflight[1] <= (waiting | inbubble) ? 0 : def_cpsr;
+               cpsr_inflight[1] <= ((waiting | inbubble) && condition_met) ? 0 : def_cpsr;
                regs_inflight[0] <= regs_inflight[1];
-               regs_inflight[1] <= (waiting | inbubble) ? 0 : def_regs;
+               regs_inflight[1] <= ((waiting | inbubble) && condition_met) ? 0 : def_regs;
 
                outbubble <= inbubble | waiting | !condition_met;
                outpc <= inpc;
                outinsn <= insn;
+               outstall <= waiting;
        end
-       
 endmodule

diff --git a/system.v b/system.v
index 0c25de3a9e3f28b6fb13212fb16fc762cf5ba39e..e33bbff1ede9eb05cfc1741006ce28a35b9e7169 100644 (file)
--- a/system.v
+++ b/system.v
@@ -32,6 +32,22 @@ module System(input clk, output wire bubbleshield, output wire [31:0] insn, outp
        wire icache_rd_req;
        wire icache_rd_wait;
        wire [31:0] icache_rd_data;
+       
+       wire stall_cause_issue;
+       
+       wire stall_in_fetch = stall_cause_issue;
+       wire stall_in_issue = 0;
+       
+       wire bubble_out_fetch;
+       wire bubble_out_issue;
+       wire [31:0] insn_out_fetch;
+       wire [31:0] insn_out_issue;
+       wire [31:0] pc_out_fetch;
+       wire [31:0] pc_out_issue;
+       
+       assign bubbleshield = bubble_out_issue;
+       assign insn = insn_out_issue;
+       assign pc = pc_out_issue;
 
        BusArbiter busarbiter(.bus_req(bus_req), .bus_ack(bus_ack));
 
@@ -56,7 +72,16 @@ module System(input clk, output wire bubbleshield, output wire [31:0] insn, outp
                .Nrst(1 /* XXX */),
                .rd_addr(icache_rd_addr), .rd_req(icache_rd_req),
                .rd_wait(icache_rd_wait), .rd_data(icache_rd_data),
-               .stall(0 /* XXX */), .jmp(0 /* XXX */), .jmppc(0 /* XXX */),
-               .bubble(bubbleshield), .insn(insn), .pc(pc));
-
+               .stall(stall_in_fetch), .jmp(0 /* XXX */), .jmppc(0 /* XXX */),
+               .bubble(bubble_out_fetch), .insn(insn_out_fetch),
+               .pc(pc_out_fetch));
+       
+       Issue issue(
+               .clk(clk),
+               .Nrst(1 /* XXX */),
+               .stall(stall_in_issue), .flush(0 /* XXX */),
+               .inbubble(bubble_out_fetch), .insn(insn_out_fetch),
+               .inpc(pc_out_fetch), .cpsr(0 /* XXX */),
+               .outstall(stall_cause_issue), .outbubble(bubble_out_issue),
+               .outpc(pc_out_issue), .outinsn(insn_out_issue));
 endmodule