Makefile: Add 'auto' target to verilog-modeify.
authorJoshua Wise <joshua@escape.joshuawise.com>
Mon, 22 Feb 2010 03:26:54 +0000 (22:26 -0500)
committerJoshua Wise <joshua@escape.joshuawise.com>
Mon, 22 Feb 2010 03:26:54 +0000 (22:26 -0500)
Makefile

index daa9291..766e6ea 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -9,4 +9,7 @@ obj_dir/Vsystem.mk: $(VLOGS)
        mkdir -p obj_dir
        verilator --cc system.v testbench.cpp --exe
 
+auto: .DUMMY
+       emacs -l ~/elisp/verilog-mode.el --batch system.v -f verilog-batch-auto
+
 .DUMMY:
\ No newline at end of file
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