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Makefile: Add 'auto' target to verilog-modeify.
author
Joshua Wise
<joshua@escape.joshuawise.com>
Mon, 22 Feb 2010 03:26:54 +0000
(22:26 -0500)
committer
Joshua Wise
<joshua@escape.joshuawise.com>
Mon, 22 Feb 2010 03:26:54 +0000
(22:26 -0500)
Makefile
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diff --git
a/Makefile
b/Makefile
index
daa9291
..
766e6ea
100644
(file)
--- a/
Makefile
+++ b/
Makefile
@@
-9,4
+9,7
@@
obj_dir/Vsystem.mk: $(VLOGS)
mkdir -p obj_dir
verilator --cc system.v testbench.cpp --exe
+auto: .DUMMY
+ emacs -l ~/elisp/verilog-mode.el --batch system.v -f verilog-batch-auto
+
.DUMMY:
\ No newline at end of file
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