ICache, Fetch: Re-pipe things such that the icache now has a one-cycle latency. ...
[firearm.git] / system.v
1 `define BUS_ICACHE 1
2 `define BUS_DCACHE 0
3
4 module System(input clk, input rst
5 `ifdef verilator
6 `else
7         , output wire [8:0] sys_odata,
8         input [8:0] sys_idata,
9         output wire sys_tookdata
10 `endif
11         );
12         
13         wire [7:0] bus_req;
14         wire [7:0] bus_ack;
15         wire [31:0] bus_addr;
16         wire [31:0] bus_rdata;
17         wire [31:0] bus_wdata;
18         wire bus_rd, bus_wr;
19         wire bus_ready;
20
21         wire bus_req_icache;
22         wire bus_req_dcache;
23         assign bus_req = {6'b0, bus_req_icache, bus_req_dcache};
24         wire bus_ack_icache = bus_ack[`BUS_ICACHE];
25         wire bus_ack_dcache = bus_ack[`BUS_DCACHE];
26         
27         wire [31:0] bus_addr_icache;
28         wire [31:0] bus_wdata_icache;
29         wire bus_rd_icache;
30         wire bus_wr_icache;
31         
32         wire [31:0] bus_addr_dcache;
33         wire [31:0] bus_wdata_dcache;
34         wire bus_rd_dcache;
35         wire bus_wr_dcache;
36         
37         wire [31:0] bus_rdata_blockram;
38         wire bus_ready_blockram;
39         
40         assign bus_addr = bus_addr_icache | bus_addr_dcache;
41         assign bus_rdata = bus_rdata_blockram;
42         assign bus_wdata = bus_wdata_icache | bus_wdata_dcache;
43         assign bus_rd = bus_rd_icache | bus_rd_dcache;
44         assign bus_wr = bus_wr_icache | bus_wr_dcache;
45         assign bus_ready = bus_ready_blockram;
46
47         wire [31:0] icache_rd_addr;
48         wire icache_rd_req;
49         wire icache_rd_wait;
50         wire [31:0] icache_rd_data;
51         
52         wire [31:0] dcache_addr;
53         wire dcache_rd_req, dcache_wr_req;
54         wire dcache_rw_wait;
55         wire [31:0] dcache_wr_data, dcache_rd_data;
56         
57         wire [31:0] decode_out_op0, decode_out_op1, decode_out_op2, decode_out_spsr, decode_out_cpsr;
58         wire decode_out_carry;
59         
60         wire [3:0] regfile_read_0, regfile_read_1, regfile_read_2, regfile_read_3;
61         wire [31:0] regfile_rdata_0, regfile_rdata_1, regfile_rdata_2, regfile_rdata_3, regfile_spsr;
62         wire regfile_write;
63         wire [3:0] regfile_write_reg;
64         wire [31:0] regfile_write_data;
65         
66         wire execute_out_write_reg;
67         wire [3:0] execute_out_write_num;
68         wire [31:0] execute_out_write_data;
69         wire [31:0] execute_out_op0, execute_out_op1, execute_out_op2;
70         wire [31:0] execute_out_cpsr, execute_out_spsr;
71         wire execute_out_cpsrup;
72         
73         wire jmp_out_execute, jmp_out_writeback;
74         wire [31:0] jmppc_out_execute, jmppc_out_writeback;
75         wire jmp = jmp_out_execute | jmp_out_writeback;
76         wire [31:0] jmppc = jmppc_out_execute | jmppc_out_writeback;
77         
78         wire memory_out_write_reg;
79         wire [3:0] memory_out_write_num;
80         wire [31:0] memory_out_write_data;
81         wire [31:0] memory_out_cpsr, memory_out_spsr;
82         wire memory_out_cpsrup;
83         
84         wire [31:0] writeback_out_cpsr, writeback_out_spsr;
85
86         wire cp_ack_terminal;
87         wire cp_busy_terminal;
88         wire [31:0] cp_read_terminal;
89         
90         wire cp_req;
91         wire [31:0] cp_insn;
92         wire cp_ack = cp_ack_terminal;
93         wire cp_busy = cp_busy_terminal;
94         wire cp_rnw;
95         wire [31:0] cp_read = cp_read_terminal;
96         wire [31:0] cp_write;
97         
98         wire stall_cause_issue;
99         wire stall_cause_execute;
100         wire stall_cause_memory;
101         wire bubble_out_fetch;
102         wire bubble_out_issue;
103         wire bubble_out_execute;
104         wire bubble_out_memory;
105         wire [31:0] insn_out_fetch;
106         wire [31:0] insn_out_issue;
107         wire [31:0] insn_out_execute;
108         wire [31:0] insn_out_memory;
109         wire [31:0] pc_out_fetch;
110         wire [31:0] pc_out_issue;
111         wire [31:0] pc_out_execute;
112         wire [31:0] pc_out_memory;
113         
114         /*AUTOWIRE*/
115         // Beginning of automatic wires (for undeclared instantiated-module outputs)
116         wire [31:0]     ic__rd_addr_0a;         // From fetch of Fetch.v
117         wire [31:0]     ic__rd_data_1a;         // From icache of ICache.v
118         wire            ic__rd_req_0a;          // From fetch of Fetch.v
119         wire            ic__rd_wait_0a;         // From icache of ICache.v
120         // End of automatics
121
122         wire execute_out_backflush;
123         wire writeback_out_backflush;
124
125         BusArbiter busarbiter(.bus_req(bus_req), .bus_ack(bus_ack));
126
127         /* XXX reset? */
128         /* ICache AUTO_TEMPLATE (
129                 .clk(clk),
130                 .bus_req(bus_req_icache),
131                 .bus_ack(bus_ack_icache),
132                 .bus_addr(bus_addr_icache),
133                 .bus_rdata(bus_rdata),
134                 .bus_wdata(bus_wdata_icache),
135                 .bus_rd(bus_rd_icache),
136                 .bus_wr(bus_wr_icache),
137                 .bus_ready(bus_ready),
138                 ); */
139         ICache icache(/*AUTOINST*/
140                       // Outputs
141                       .ic__rd_wait_0a   (ic__rd_wait_0a),
142                       .ic__rd_data_1a   (ic__rd_data_1a[31:0]),
143                       .bus_req          (bus_req_icache),        // Templated
144                       .bus_addr         (bus_addr_icache),       // Templated
145                       .bus_wdata        (bus_wdata_icache),      // Templated
146                       .bus_rd           (bus_rd_icache),         // Templated
147                       .bus_wr           (bus_wr_icache),         // Templated
148                       // Inputs
149                       .clk              (clk),                   // Templated
150                       .ic__rd_addr_0a   (ic__rd_addr_0a[31:0]),
151                       .ic__rd_req_0a    (ic__rd_req_0a),
152                       .bus_ack          (bus_ack_icache),        // Templated
153                       .bus_rdata        (bus_rdata),             // Templated
154                       .bus_ready        (bus_ready));            // Templated
155         
156         DCache dcache(
157                 .clk(clk),
158                 .addr(dcache_addr), .rd_req(dcache_rd_req), .wr_req(dcache_wr_req),
159                 .rw_wait(dcache_rw_wait), .wr_data(dcache_wr_data), .rd_data(dcache_rd_data),
160                 .bus_req(bus_req_dcache), .bus_ack(bus_ack_dcache),
161                 .bus_addr(bus_addr_dcache), .bus_rdata(bus_rdata),
162                 .bus_wdata(bus_wdata_dcache), .bus_rd(bus_rd_dcache),
163                 .bus_wr(bus_wr_dcache), .bus_ready(bus_ready));
164
165 `ifdef verilator
166         BigBlockRAM
167 `else
168         BlockRAM
169 `endif
170         blockram(
171                 .clk(clk),
172                 .bus_addr(bus_addr), .bus_rdata(bus_rdata_blockram),
173                 .bus_wdata(bus_wdata), .bus_rd(bus_rd), .bus_wr(bus_wr),
174                 .bus_ready(bus_ready_blockram));
175
176         /* Fetch AUTO_TEMPLATE (
177                 .clk(clk),
178                 .Nrst(~rst),
179                 .stall_0a(stall_cause_issue),
180                 .jmp_0a(jmp),
181                 .jmppc_0a(jmppc),
182                 .bubble_1a(bubble_out_fetch),
183                 .insn_1a(insn_out_fetch),
184                 .pc_1a(pc_out_fetch),
185                 );
186         */
187         Fetch fetch(
188                 /*AUTOINST*/
189                     // Outputs
190                     .ic__rd_addr_0a     (ic__rd_addr_0a[31:0]),
191                     .ic__rd_req_0a      (ic__rd_req_0a),
192                     .bubble_1a          (bubble_out_fetch),      // Templated
193                     .insn_1a            (insn_out_fetch),        // Templated
194                     .pc_1a              (pc_out_fetch),          // Templated
195                     // Inputs
196                     .clk                (clk),                   // Templated
197                     .Nrst               (~rst),                  // Templated
198                     .ic__rd_wait_0a     (ic__rd_wait_0a),
199                     .ic__rd_data_1a     (ic__rd_data_1a[31:0]),
200                     .stall_0a           (stall_cause_issue),     // Templated
201                     .jmp_0a             (jmp),                   // Templated
202                     .jmppc_0a           (jmppc));                // Templated
203         
204         Issue issue(
205                 .clk(clk),
206                 .Nrst(~rst),
207                 .stall(stall_cause_execute), .flush(execute_out_backflush | writeback_out_backflush),
208                 .inbubble(bubble_out_fetch), .insn(insn_out_fetch),
209                 .inpc(pc_out_fetch), .cpsr(writeback_out_cpsr),
210                 .outstall(stall_cause_issue), .outbubble(bubble_out_issue),
211                 .outpc(pc_out_issue), .outinsn(insn_out_issue));
212         
213         RegFile regfile(
214                 .clk(clk), .Nrst(~rst),
215                 .read_0(regfile_read_0), .read_1(regfile_read_1), .read_2(regfile_read_2), .read_3(regfile_read_3),
216                 .rdata_0(regfile_rdata_0), .rdata_1(regfile_rdata_1), .rdata_2(regfile_rdata_2), .rdata_3(regfile_rdata_3),
217                 .spsr(regfile_spsr),
218                 .write(regfile_write), .write_reg(regfile_write_reg), .write_data(regfile_write_data));
219         
220         Decode decode(
221                 .clk(clk),
222                 .stall(stall_cause_execute),
223                 .insn(insn_out_fetch), .inpc(pc_out_fetch), .incpsr(writeback_out_cpsr), .inspsr(writeback_out_spsr),
224                 .op0(decode_out_op0), .op1(decode_out_op1), .op2(decode_out_op2),
225                 .carry(decode_out_carry), .outcpsr(decode_out_cpsr), .outspsr(decode_out_spsr),
226                 .read_0(regfile_read_0), .read_1(regfile_read_1), .read_2(regfile_read_2), 
227                 .rdata_0(regfile_rdata_0), .rdata_1(regfile_rdata_1), .rdata_2(regfile_rdata_2));
228         
229         Execute execute(
230                 .clk(clk), .Nrst(~rst),
231                 .stall(stall_cause_memory), .flush(writeback_out_backflush),
232                 .inbubble(bubble_out_issue), .pc(pc_out_issue), .insn(insn_out_issue),
233                 .cpsr(decode_out_cpsr), .spsr(decode_out_spsr), .op0(decode_out_op0), .op1(decode_out_op1),
234                 .op2(decode_out_op2), .carry(decode_out_carry),
235                 .outstall(stall_cause_execute), .outbubble(bubble_out_execute),
236                 .write_reg(execute_out_write_reg), .write_num(execute_out_write_num),
237                 .write_data(execute_out_write_data),
238                 .jmp(jmp_out_execute), .jmppc(jmppc_out_execute),
239                 .outpc(pc_out_execute), .outinsn(insn_out_execute),
240                 .outop0(execute_out_op0), .outop1(execute_out_op1), .outop2(execute_out_op2),
241                 .outcpsr(execute_out_cpsr), .outspsr(execute_out_spsr), .outcpsrup(execute_out_cpsrup));
242         assign execute_out_backflush = jmp;
243         
244         assign cp_insn = insn_out_execute;
245         Memory memory(
246                 .clk(clk), .Nrst(~rst),
247                 /* stall? */ .flush(writeback_out_backflush),
248                 .busaddr(dcache_addr), .rd_req(dcache_rd_req), .wr_req(dcache_wr_req),
249                 .rw_wait(dcache_rw_wait), .wr_data(dcache_wr_data), .rd_data(dcache_rd_data),
250                 .st_read(regfile_read_3), .st_data(regfile_rdata_3),
251                 .inbubble(bubble_out_execute), .pc(pc_out_execute), .insn(insn_out_execute),
252                 .op0(execute_out_op0), .op1(execute_out_op1), .op2(execute_out_op2),
253                 .spsr(execute_out_spsr), .cpsr(execute_out_cpsr), .cpsrup(execute_out_cpsrup),
254                 .write_reg(execute_out_write_reg), .write_num(execute_out_write_num), .write_data(execute_out_write_data),
255                 .outstall(stall_cause_memory), .outbubble(bubble_out_memory), 
256                 .outpc(pc_out_memory), .outinsn(insn_out_memory),
257                 .out_write_reg(memory_out_write_reg), .out_write_num(memory_out_write_num), 
258                 .out_write_data(memory_out_write_data),
259                 .cp_req(cp_req), .cp_ack(cp_ack), .cp_busy(cp_busy), .cp_rnw(cp_rnw), .cp_read(cp_read), .cp_write(cp_write),
260                 .outcpsr(memory_out_cpsr), .outspsr(memory_out_spsr), .outcpsrup(memory_out_cpsrup) /* XXX data_size */);
261         
262         Terminal terminal(      
263                 .clk(clk),
264                 .cp_req(cp_req), .cp_insn(cp_insn), .cp_ack(cp_ack_terminal), .cp_busy(cp_busy_terminal), .cp_rnw(cp_rnw),
265                 .cp_read(cp_read_terminal), .cp_write(cp_write)
266 `ifdef verilator
267 `else
268                 , .sys_odata(sys_odata), .sys_tookdata(sys_tookdata), .sys_idata(sys_idata)
269 `endif
270                 );
271         
272         Writeback writeback(
273                 .clk(clk),
274                 .inbubble(bubble_out_memory),
275                 .write_reg(memory_out_write_reg), .write_num(memory_out_write_num), .write_data(memory_out_write_data),
276                 .cpsr(memory_out_cpsr), .spsr(memory_out_spsr), .cpsrup(memory_out_cpsrup),
277                 .regfile_write(regfile_write), .regfile_write_reg(regfile_write_reg), .regfile_write_data(regfile_write_data),
278                 .outcpsr(writeback_out_cpsr), .outspsr(writeback_out_spsr), 
279                 .jmp(jmp_out_writeback), .jmppc(jmppc_out_writeback));
280         assign writeback_out_backflush = jmp_out_writeback;
281
282         reg [31:0] clockno = 0;
283         always @(posedge clk)
284         begin
285                 clockno <= clockno + 1;
286                 $display("------------------------------------------------------------------------------");
287                 $display("%3d: FETCH:            Bubble: %d, Instruction: %08x, PC: %08x", clockno, bubble_out_fetch, insn_out_fetch, pc_out_fetch);
288                 $display("%3d: ISSUE:  Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x", clockno, stall_cause_issue, bubble_out_issue, insn_out_issue, pc_out_issue);
289                 $display("%3d: DECODE:                      op0 %08x, op1 %08x, op2 %08x, carry %d", clockno, decode_out_op0, decode_out_op1, decode_out_op2, decode_out_carry);
290                 $display("%3d: EXEC:   Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x, Reg: %d, [%08x -> %d], Jmp: %d [%08x]", clockno, stall_cause_execute, bubble_out_execute, insn_out_execute, pc_out_execute, execute_out_write_reg, execute_out_write_data, execute_out_write_num, jmp_out_execute, jmppc_out_execute);
291                 $display("%3d: MEMORY: Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x, Reg: %d, [%08x -> %d]", clockno, stall_cause_memory, bubble_out_memory, insn_out_memory, pc_out_memory, memory_out_write_reg, memory_out_write_data, memory_out_write_num);
292                 $display("%3d: WRITEB:                      CPSR %08x, SPSR %08x, Reg: %d [%08x -> %d], Jmp: %d [%08x]", clockno, writeback_out_cpsr, writeback_out_spsr, regfile_write, regfile_write_data, regfile_write_reg, jmp_out_writeback, jmppc_out_writeback);
293         end
294 endmodule
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