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(parent: fd003c7) | patch
DCache, ICache: Make cache_data a 1-D array to enable better synthesizability on...
authorJoshua Wise <joshua@rebirth.joshuawise.com>
Sat, 24 Jan 2009 10:37:43 +0000 (05:37 -0500)
committerJoshua Wise <joshua@rebirth.joshuawise.com>
Sat, 24 Jan 2009 10:37:43 +0000 (05:37 -0500)
commit2b5c79c05898ff20b0c04cd78bccb2580f6c8331
treea823f954a5c0bbf5d0765315e5f8e05232b3de84tree | snapshot
parentfd003c7a793fb17fb6dc7ba52873b883b28a578bcommit | diff
DCache, ICache: Make cache_data a 1-D array to enable better synthesizability on Xilinx.
BlockRAM.v diff | blob | blame | history
DCache.v diff | blob | blame | history
ICache.v diff | blob | blame | history
ram.hex diff | blob | blame | history
FireARM pipelined ARM-like CPU implementation in Verilog
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