DCache, ICache: Make cache_data a 1-D array to enable better synthesizability on...
[firearm.git] / BlockRAM.v
index e0eceeb..091c749 100644 (file)
@@ -31,11 +31,11 @@ module BlockRAM(
        always @(posedge clk)
        begin
                if (bus_wr && decode)
-                       data[ramaddr[13:2]] = bus_wdata;
+                       data[ramaddr[13:2]] <= bus_wdata;
                
                /* This is not allowed to be conditional -- stupid Xilinx
                 * blockram. */
-               temprdata <= data[ramaddr[13:2]];
+               temprdata <= (bus_wr && decode) ? bus_wdata : data[ramaddr[13:2]];
                lastread <= ramaddr;
        end
 endmodule
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