From 2393422aab14e1b2172b4e52b9117272cc13c72e Mon Sep 17 00:00:00 2001
From: Joshua Wise <joshua@rebirth.joshuawise.com>
Date: Mon, 5 Jan 2009 22:21:53 -0500
Subject: [PATCH] Execute.v: Add outpc and outinsn. System.v: Add and make
 wires consistent.

---
 Execute.v |  6 +++++-
 system.v  | 12 +++++++-----
 2 files changed, 12 insertions(+), 6 deletions(-)

diff --git a/Execute.v b/Execute.v
index 8a7d8f6..cd71d76 100644
--- a/Execute.v
+++ b/Execute.v
@@ -23,7 +23,9 @@ module Execute(
 	output reg [3:0] write_num = 4'bxxxx,
 	output reg [31:0] write_data = 32'hxxxxxxxx,
 	output reg [31:0] jmppc,
-	output reg jmp
+	output reg jmp,
+	output reg [31:0] outpc,
+	output reg [31:0] outinsn
 	);
 	
 	reg mult_start;
@@ -65,6 +67,8 @@ module Execute(
 			write_reg <= next_write_reg;
 			write_num <= next_write_num;
 			write_data <= next_write_data;
+			outpc <= pc;
+			outinsn <= insn;
 		end
 	end
 
diff --git a/system.v b/system.v
index 4601ae7..6fd0b8b 100644
--- a/system.v
+++ b/system.v
@@ -40,7 +40,6 @@ module System(input clk);
 	wire decode_out_carry;
 	wire [3:0] regfile_read_0, regfile_read_1, regfile_read_2;
 	wire [31:0] regfile_rdata_0, regfile_rdata_1, regfile_rdata_2, regfile_spsr;
-	wire execute_out_stall, execute_out_bubble;
 	wire execute_out_write_reg;
 	wire [3:0] execute_out_write_num;
 	wire [31:0] execute_out_write_data;
@@ -49,10 +48,13 @@ module System(input clk);
 	
 	wire bubble_out_fetch;
 	wire bubble_out_issue;
+	wire bubble_out_execute;
 	wire [31:0] insn_out_fetch;
 	wire [31:0] insn_out_issue;
+	wire [31:0] insn_out_execute;
 	wire [31:0] pc_out_fetch;
 	wire [31:0] pc_out_issue;
+	wire [31:0] pc_out_execute;
 
 	wire execute_out_backflush;
 
@@ -112,11 +114,11 @@ module System(input clk);
 		.inbubble(bubble_out_issue), .pc(pc_out_issue), .insn(insn_out_issue),
 		.cpsr(32'b0 /* XXX */), .spsr(decode_out_spsr), .op0(decode_out_op0), .op1(decode_out_op1),
 		.op2(decode_out_op2), .carry(decode_out_carry),
-		.outstall(stall_cause_execute), .outbubble(execute_out_bubble),
+		.outstall(stall_cause_execute), .outbubble(bubble_out_execute),
 		.write_reg(execute_out_write_reg), .write_num(execute_out_write_num),
 		.write_data(execute_out_write_data),
-		.jmppc(jmppc),
-		.jmp(jmp));
+		.jmp(jmp), .jmppc(jmppc),
+		.outpc(pc_out_execute), .insn(insn_out_execute));
 	assign execute_out_backflush = jmp;
 
 	reg [31:0] clockno = 0;
@@ -127,6 +129,6 @@ module System(input clk);
 		$display("%3d: FETCH:            Bubble: %d, Instruction: %08x, PC: %08x", clockno, bubble_out_fetch, insn_out_fetch, pc_out_fetch);
 		$display("%3d: ISSUE:  Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x", clockno, stall_cause_issue, bubble_out_issue, insn_out_issue, pc_out_issue);
 		$display("%3d: DECODE:                      op1 %08x, op2 %08x, op3 %08x, carry %d", clockno, decode_out_op0, decode_out_op1, decode_out_op2, decode_out_carry);
-		$display("%3d: EXEC:   Stall: %d, Bubble: %d, Reg: %d, [%08x -> %d], Jmp: %d [%08x]", clockno, stall_cause_execute, execute_out_bubble, execute_out_write_reg, execute_out_write_data, execute_out_write_num, jmp, jmppc);
+		$display("%3d: EXEC:   Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x, Reg: %d, [%08x -> %d], Jmp: %d [%08x]", clockno, stall_cause_execute, bubble_out_execute, insn_out_execute, pc_out_execute, execute_out_write_reg, execute_out_write_data, execute_out_write_num, jmp, jmppc);
 	end
 endmodule
-- 
2.39.2